13-BIT 250 MSPS ANALOG-TO-DIGITAL CONVERTER

ADS5444 www.ti.com SLWS162A – AUGUST 2005 – REVISED FEBRUARY 2006 13-BIT 250 MSPS ANALOG-TO-DIGITAL CONVERTER FEATURES • • • • • • • • • • • • • • • 13-Bit Resolution 250 MSPS Sample Rate SNR = 69 dBc at 100-MHz IF and 250 MSPS SFDR = 76 dBc at 100-MHz IF and 250 MSPS SNR = 67.7 dBc at 230-MHz IF and 250 MSPS SFDR = 77 dBc at 230-MHz IF and 250 MSPS 2.2 VPP Differential Input Voltage Fully Buffered Analog Inputs 5 V Analog Supply Voltage LVDS Compatible Outputs Total Power Dissipation: 2 W Offset Binary Output Format TQFP-80 PowerPAD™ Package Pin Compatible with the ADS5440 Industrial Temperature Range = –40°C to 85°C APPLICATIONS • • • • • • • • Test and Measurement Software-Defined Radio Multi-channel Basestation Receivers Basestation Tx Digital Predistortion Communications Instrumentation RELATED PRODUCTS ADS5424 - 14-bit, 105 MSPS ADC ADS5423 - 14-bit, 80 MSPS ADC ADS5440 - 13-bit, 210 MSPS ADC DESCRIPTION www.DataSheet4U.com The ADS5444 is a 13-bit 250 MSPS analog-to-digital converter (ADC) that operates from a 5 V supply, while providing LVDS-compatible digital outputs from a 3.3 V supply. The ADS5444 input buffer isolates the internal switching of the onboard track and hold (T&H) from disturbing the signal source. An internal reference generator is also provided to further simplify the system design. The ADS5444 has outstanding low noise and linearity over input frequency. AVDD AIN AIN + DVDD A1 TH1 TH2 Σ − A2 TH3 + − Σ A3 ADC3 ADC1 DAC1 ADC2 DAC2 VREF Reference 5 Digital Error Correction 5 5 CLK CLK Timing OVR OVR DRY DRY D[12:0] GND B0061-01 The ADS5444 is available in an 80-pin TQFP PowerPAD™ package. The ADS5444 is built on a state of the art Texas Instruments complementary bipolar process (BiCom3X) and is specified over the full industrial temperature range (–40°C to 85°C). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2006, Texas Instruments Incorporated ADS5444 SLWS162A – AUGUST 2005 – REVISED FEBRUARY 2006 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGING/ORDERING INFORMATION (1) Product PackageLead HTQFP-80 (2) PowerPAD Package Designator (1) Specified Temperature Range –40°C to 85°C Package Marking Ordering Number ADS5444IPFP ADS5444IPFPR Transport Media, Quantity Tray, 96 Tape and Reel, 1000 ADS5444 (1) (2) PFP ADS5444IPFP For the most current product and ordering information, see the Package Option Addendum located at the end of this document, or see the TI website at www.ti.com. Thermal pad size: 7,5 mm x 7,5 mm (typ) ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE / UNIT Supply voltage Analog input to GND Clock input to GND CLK to CLK Digital data output to GND Operating temperature range Maximum junction temperature Storage temperature range ESD Human Body Model (HBM) (1) AVDD to GND DRVDD to GND 6V 5V –0.3 V to AVDD+0.3 V –0.3 V to AVDD+0.3 V ±2.5 V –0.3 V to DRVDD+0.3 V –40°C to 85°C 150°C –65°C to 150°C 2.5 kV Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only and functional operation of the device at these or any other conditions beyond those specified is not implied. THERMAL CHARACTERISTICS (1) PARAMETER Soldered slug, no airflow θJA Soldered slug, 250-LFPM airflow Unsoldered slug, no airflow Unsoldered slug, 250-LFPM airflow θJC (1) Bottom of package (heatslug) TEST CONDITIONS TYP 21.7 15.4 50 43.4 2.99 UNIT °C/W °C/W °C/W °C/W °C/W Using 36 thermal vias (6 x 6 array). See the Application Section. 2 Submit Documentation Feedback www.ti.com ADS5444 SLWS162A – AUGUST 2005 – REVISED FEBRUARY 2006 RECOMMENDED OPERATING CONDITIONS MIN SUPPLIES AVDD DRVDD Analog supply voltage Output driver supply voltage Differential input range VCM 1/tC Input common mode ADCLK input sample rate (sine wave) Clock amplitude, differential sine wave Clock duty cycle TA Open free air temperature –40 10 3 50% 85 °C CLOCK INPUT 250 MSPS Vpp 4.75 3 5 3.3 2.2 2.4 5.25 3.6 V V VPP V NOM MAX UNIT ANALOG INPUT ELECTRICAL CHARACTERISTICS MIN, TYP, and MAX values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1 dBFS differential input, and 3 VPP differential clock, unless otherwise noted PARAMETER Resolution ANALOG INPUTS Differential input range Differential input resistance (DC) Differential input capacitance Analog input bandwidth INTERNAL REFERENCE VOLTAGE VREF Reference voltage No missing codes DNL INL Differential linearity error Integral linearity error Offset error Offset temperature coefficient Gain error Gain temperature coefficient PSRR POWER SUPPLY IAVDD IDRVDD Analog supply current Output buffer supply current Power dissipation VIN = full scale, fIN = 100 MHz, FS = 250 MSPS 340 80 2 390 100 2.28 mA mA W 100-MHz supply frequency –5 -0.02 1 fIN = 10 MHz fIN = 10 MHz -1 -2.2 -11 0.0005 5 2.4 Assured ±0.4 ±0.9 1 2.2 11 LSB LSB mV mV/°C %FS ∆%/°C mV/V V DYNAMIC ACCURACY 2.2 1 1.5 800 Vpp kΩ pF MHz TEST CONDITIONS MIN TYP 13 MAX UNIT Bits Submit Documentation Feedback 3 ADS5444 SLWS162A – AUGUST 2005 – REVISED FEBRUARY 2006 www.ti.com ELECTRICAL CHARACTERISTICS (continued) MIN, TYP, and MAX values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1 dBFS differential input, and 3 VPP differential clock, unless otherwise noted PARAMETER DYNAMIC AC CHARACTERISTICS fIN = 10 MHz fIN = 70 MHz fIN = 100 MHz SNR Signal-to-noise ratio fIN = 170 MHz fIN = 230 MHz fIN = 300 MHz fIN = 400 MHz fIN = 10 MHz fIN = 70 MHz fIN = 100 MHz SFDR Spurious free dynamic range fIN = 170 MHz fIN = 230 MHz fIN = 300 MHz fIN = 400 MHz fIN = 10 MHz fIN = 70 MHz fIN = 100 MHz HD2 Second harmonic fIN = 170 MHz fIN = 230 MHz fIN = 300 MHz fIN = 400 MHz fIN = 10 MHz fIN = 70 MHz fIN = 100 MHz HD3 Third harmonic fIN = 170 MHz fIN = 230 MHz fIN = 300 MHz fIN = 400 MHz fIN = 10 MHz fIN = 70 MHz Worst other harmonic/spur (other than HD2 and HD3) fIN = 100 MHz fIN = 170 MHz fIN = 230 MHz fIN = 300 MHz fIN = 400 MHz TA = 25°C Full Temp Range 70 68 TA = 25°C Full Temp Range 67 66.5 69.3 69 69 69 68.3 67.7 67 66 85 77 77 77 74 77 70 64 87 77 80 74 78 70 64 86 82 79 80 91 80 69 90 95 82 80 83 86 85 dBc dBc dBc dBc dBc TEST CONDITIONS MIN TYP MAX UNIT 4 Submit Documentation Feedback www.ti.com ADS5444 SLWS162A – AUGUST 2005 – REVISED FEBRUARY 2006 ELECTRICAL CHARACTERISTICS (continued) MIN, TYP, and MAX values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1 dBFS differential input, and 3 VPP differential clock, unless otherwise noted PARAMETER fIN = 10 MHz fIN = 70 MHz fIN = 100 MHz SINAD fIN = 170 MHz fIN = 230 MHz fIN = 300 MHz fIN = 400 MHz ENOB Effective number of bits RMS idle channel noise Differential output voltage Output offset voltage fIN = 10 MHz Inputs tied to common-mode 0.247 1.125 1.25 TEST CONDITIONS MIN TYP 69 68 67.6 66.5 67 65 61 11.2 0.4 0.452 1.375 Bits LSB V V dBc MAX UNIT DIGITAL CHARACTERISTICS – LVDS DIGITAL OUTPUTS Submit Documentation Feedback 5 ADS5444 SLWS162A – AUGUST 2005 – REVISED FEBRUARY 2006 www.ti.com TIMING CHARACTERISTICS tA N N+3 AIN N+1 N+2 tCLK CLK, CLK N tCLKH N+1 tCLKL N+2 tC_DR N+3 tsu_c N+4 N+4 th_c D[12:0], OVR, OVR tr DRY, DRY N−3 tf N−2 tsu_DR N−1 th_DR N tDR T0073-01 Figure 1. Timing Diagram TIMING CHARACTERISTICS Min, Typ, Max over full temperature range, 50% clock duty cycle, sampling rate = 250 MSPS, AVDD = 5 V, DRVDD = 3.3 V PARAMETER tA tJ Clock Input tCLK tCLKH tCLKL tDR tC_DR tr tf tsu_c th_c tsu(DR) th(DR) (1) (2) 6 Clock period Clock pulsewidth high Clock pulsewidth low Clock rising to DataReady falling Clock rising to DataReady rising Data rise time (20% to 80%) Data fall time(80% to 20%) Data valid to clock (setup time) Clock to invalid Data (hold time) Data valid to DRY DRY to invalid Data 1.7 0.9 Clock duty cycle = 50% (1) TEST CONDITIONS MIN TYP 500 200 4 4 2 2 1.1 MAX UNIT ps fs RMS cycles ns ns ns ns Aperature delay Clock slope independent aperture uncertainty (jitter) Latency Clock to DataReady (DRY) 2.7 3.1 0.6 0.6 3.1 0.2 2 1.3 3.5 ns ns ns ns ns ns ns Clock to DATA, OVR (2) DataReady (DRY)/DATA, OVR (2) tC_DR = tDR + tCLKH for clock duty cycles other than 50% Data is updated with clock falling edge or DRY rising edge. Submit Documentation Feedback www.ti.com ADS5444 SLWS162A – AUGUST 2005 – REVISED FEBRUARY 2006 DEVICE INFORMATION PFP PACKAGE (TOP VIEW) D5 D5 D6 D6 GND DVDD D7 D7 D8 D8 D9 D9 D10 D10 D11 D11 D12 D12 DRY DRY 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 DV