CMOS Multimedia Switch

Low Voltage, CMOS Multimedia Switch ADG790 FEATURES Single-chip audio/video/data switching solution Wide bandwidth section Rail-to-rail signal switching capability Compliant with full speed USB 2.0 signaling (3.6 V p-p) Compliant with high speed USB 2.0 signaling (400 mV p-p) Supports USB data rates up to 480 Mbps 550 MHz, 3 dB bandwidth Low RON: 5.9 Ω typical Excellent matching between channels Low distortion section Low RON: 3.9 Ω typical 230 MHz, 3 dB bandwidth (SPDT) 160 MHz, 3 dB bandwidth (4:1 multiplexers) Single-supply operation: 1.65 V to 3.6 V Typical power consumption: <0.1 μW Pb-free packaging: 30-ball WLCSP (3 mm × 2.5 mm) FUNCTIONAL BLOCK DIAGRAM ADG790 WIDE BANDWIDTH SECTION LOW DISTORTION SECTION S5A S5B S1A S1B D1 S2A S2B D2 S3A S3B D3 S5C S5D D5 S6A S6B S6C S6D D6 S4A S4B D4 DECODER 06357-001 APPLICATIONS Cellular phones PMPs www.DataSheet4U.com MP3 players Audio/video/data/USB switching VDD IN1 IN2 IN3 S/D GND Figure 1. GENERAL DESCRIPTION The ADG790 is a single-chip, CMOS switching solution that comprises four SPDT switches and two 4:1 multiplexers. The internal architecture of the device provides two switching sections, a wide bandwidth section and a low distortion section. The wide bandwidth section contains three SPDT switches that exhibit low on resistance with excellent flatness and channel matching. This, combined with wide bandwidth, makes the three-SPDT-switch configuration ideal for high frequency signals, such as full speed (12 Mbps) and high speed (480 Mbps) USB signals and high resolution video signals. The low distortion section contains a single SPDT switch and two 4:1 multiplexers that exhibit very low on resistance and excellent flatness, making these switches ideal for a wide range of applications, including low distortion audio applications and low resolution video (CVBS and S-Video) applications. All switches conduct equally well in both directions when on and block signals up to the supply rails when off. A 4-wire parallel interface controls the operation of the device and allows the user to control switches from both sections simultaneously. This simplifies the design and provides a cost-effective, single-chip switching solution for portable devices where multiple signals share a single port connector. The shutdown (S/D) pin allows the user to disable all four SPDT switches and force the 4:1 multiplexers into the S5B and S6B positions, respectively. The ADG790 is packaged in a compact, 30-ball WLCSP (6 × 5 ball array) with a total area of 7.5 mm2 (3 mm × 2.5 mm). This tiny package size and its low power consumption make the ADG790 an ideal solution for portable devices. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. ADG790 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Terminology ...................................................................................... 7 Typical Performance Characteristics ............................................. 8 Test Circuits..................................................................................... 11 Theory of Operation ...................................................................... 13 Wide Bandwidth Section........................................................... 13 Low Distortion Section.............................................................. 13 Control Interface ........................................................................ 13 Evaluation Board ............................................................................ 14 Using the ADG790 Evaluation Board ..................................... 14 Outline Dimensions ....................................................................... 17 Ordering Guide .......................................................................... 17 REVISION HISTORY 1/07—Revision 0: Initial Version Rev. 0 | Page 2 of 20 ADG790 SPECIFICATIONS VDD = 2.7 V to 3.6 V, GND = 0 V, TA = –40°C to +85°C, all switch sections unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance Symbol Test Conditions/Comments Min 0 RON VDD = 2.7 V, VS = 0 V to VDD, IDS = 10 mA (see Figure 18) Wide bandwidth section 2 Low distortion section 3 VDD = 2.7 V, VS = 0 V to VDD, IDS = 10 mA (see Figure 18) Wide bandwidth section2 Low distortion section3 VDD = 2.7 V, VS = 0 V to VDD, IDS = 10 mA Wide bandwidth section2 Low distortion section3 (SPDT) Low distortion section3 (4:1 multiplexers) LEAKAGE CURRENTS Source Off Leakage Channel On Leakage DIGITAL INPUTS (IN1, IN2, IN3, S/D) Input High Voltage Input Low Voltage Input High/Input Low Current Digital Input Capacitance DYNAMIC CHARACTERISTICS 5 tON tOFF Propagation Delay IS (OFF) ID, IS (ON) VINH VINL IINL, IINH CIN tON tOFF tD VDD = 3.6 V, VS = 0 V or 3.6 V, VD = 3.6 V or 0 V (see Figure 19) VDD = 3.6 V, VS = VD = 0 V or 3.6 V (see Figure 20) 2.0 VIN = VINL or VINH ±0.005 6 20 9 0.3 0.65 0.4 20 40 11 –0.57 6.2 –74 –77 1.2 0.65 550 230 160 0.07 0.08 0.18 0.8 ±0.1 5.9 3.9 2.0 0.74 Typ 1 Max VDD 8.8 5.5 3.6 1.6 Unit V Ω Ω Ω Ω On Resistance Flatness RFLAT(ON) On Resistance Matching Between Channels 4 ∆RON 0.52 0.1 0.3 Ω Ω Ω ±10 ±10 nA nA V V μA pF ns ns ns ns ns ps ps ns pC pC dB dB % % MHz MHz MHz % % % Propagation Delay Skew tSKEW Break-Before-Make Time Delay Charge Injection tBBM QINJ Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion THD + N –3 dB Bandwidth Differential Gain Error RL = 50 Ω, CL = 35 pF, VS = VDD/2 or 0 V (see Figure 24) RL = 50 Ω, CL = 35 pF, VS = VDD/2 or 0 V (see Figure 24) RL = 50 Ω, CL = 35 pF Wide bandwidth section2 Low distortion section3 (SPDT) Low distortion section3 (4:1 multiplexers) RL = 50 Ω, CL = 35 pF Wide bandwidth section2 Low distortion section3 (4:1 multiplexers) RL = 50 Ω, CL = 35 pF, VS1 = VS2 = VDD/2 (see Figure 25) VS = 0 V, RS = 0 Ω, CL = 1 nF (see Figure 26) Wide bandwidth section2 Low distortion section3 RL = 50 Ω, CL = 5 pF, f = 1 MHz (see Figure 21) RL = 50 Ω, CL = 5 pF, f = 1 MHz (see Figure 22) RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 2 V p-p Wide bandwidth section2 Low distortion section3 RL = 50 Ω, CL = 5 pF (see Figure 23) Wide bandwidth section2 Low distortion section3 (SPDT) Low distortion section3 (4:1 multiplexers) CCIR330 test signal Wide bandwidth section2 Low distortion section3 (SPDT) Low distortion section3 (4:1 multiplexers) Rev. 0 | Page 3 of 20 32 15 0.46 0.95 0.65 5 ADG790 Parameter Differential Phase Error Symbol Test Conditions/Comments CCIR330 test signal Wide bandwidth section2 Low distortion section3 (SPDT) Low distortion section3 (4:1 multiplexers) f= 10 kHz, no decoupling capacitors Wide bandwidth section2 Low distortion section3 Wide bandwidth section2 Low distortion section3 (SPDT) Wide bandwidth section2 Low distortion section3 (SPDT) Low distortion section3 (4:1 multiplexers) Min Typ 1 0.13 0.08 0.19 –90 3.5 11 5.5 14 8.5 19 32 1.65 VDD = 3.6 V, digital inputs tied to 0 V or 3.6 V 0.1 3.6 1 Max Unit Degrees Degrees Degrees dB pF pF pF pF pF pF pF V μA Power Supply Rejection Ratio Source Off Capacitance Drain Off Capacitance Source/Drain On Capacitance PSRR CS (OFF) CD (OFF) CD, CS (ON) POWER REQUIREMENTS Supply Voltage Supply Current 1 2 VDD IDD All typical values are at TA = 25°C, VDD = 3.3 V. Refers to all switches connected to Pin D1, Pin D2, and Pin D3. 3 Refers to all switches connected to Pin D4 (SPDT), Pin D5, and Pin D6 (4:1 multiplexers). 4 Refers to the on resistance matching between the same channels (SxA and SxB, for example) from different multiplexers for the wide bandwidth section and the 4:1 multiplexers from the low distortion section. For the SPDT switch from the low distortion section, it refers to the matching between the S4A and S4B channels. 5 Guaranteed by design; not subject to production test. Rev. 0 | Page 4 of 20 ADG790 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 2. Parameter VDD to GND Analog and Digital Pins1 Peak Current, S or D Continuous Current, S or D Operating Temperature Range Storage Temperature Range Junction Temperature Thermal Impedance (θJA)2 Reflow Soldering (Pb Free) Peak Temperature Time at Peak Temperature 1 Rating –0.3 V to +4.6 V –0.3 V to VDD + 0.3 V or 10 mA, whichever occurs first 100 mA (pulsed at 1 ms, 10% duty cycle maximum) 30 mA –40°C to +85°C –65°C to +125°C 150°C 80°C/W 260°C (+0°C/–5°C) As per JEDEC J-STD-20 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rati