High Speed 14-Bit 1MHz Sampling A/D Converter

www.DataSheet4U.com ADC3214 High Speed, 14-Bit, 1 MHz, Sampling A/D Converter With Built-in Sample-and-Hold Amplifier Introduction The ADC3214 is a 14-bit, 1 MHz A/D converter with a built-in sampleand-hold amplifier. It was designed for use in applications requiring high speed and high resolution front ends, such as ATE, medical imaging, radar, communications, and analytical instrumentation. The ADC3214 is a cost-effective solution for both time and frequency domain applications. It is capable of digitizing a 500 kHz signal at a 1 MHz rate with a guarantee of no missing codes. Signal-to-noise ratio is 76 dB at input frequencies from DC to 100 kHz. With a 1 MHz sampling rate and a full-scale step response to 14-bit accuracy of one conversion, this sampling A/D converter is ideally suited for applications with multiplexed signal sources. The ADC3214 utilizes the latest surface-mount technologies to produce a cost-effective, high-performance part in a 2" x 3" fully shielded package. It is designed around a two-pass, subranging architecture that integrates a low distortion sample-and-hold amplifier, precision voltage reference, all the necessary timing circuitry and tri-state CMOS/TTL-compatible outputs for ease of system integration. Continued on page 3. Features u u u u u u u u 14-Bit Resolution 1 MHz Throughput Rate Reduced Cost Reduced Size No Missing Codes: 0°C to +60°C Signal-to-Noise Ratio: 76 dB Peak Distortion: –82 dB @ 100 kHz Total Harmonic Distortion: –80 dB @ 100 kHz Ease of Use Built-In S/H Amplifier TTL Compatibility High Input Impedance (100 MΩ) Signal In S/H Amplifier P1 P2 +15V Ana. Rtn. –15V +5V Dig. Rtn. u u u u Range 1 Range 2 S/H Out A/D In Scaling & Offset Circuit Applications 8-Bit ADC ADC Clk. Ref. L o g i c Ext. Off Adj. Ext. Gain Adj. +Ref. Out Ref. Ckt. B1-B14 ∑ Ref. 4-Bit Linear DAC O/U Flow EOC Trigger Enable u u u u u u u u Radar Analytical Instrumentation Spectroscopy Digital Telecommunications Automatic Test Equipment High-Resolution Imaging Medical Data Acquisition Multiplexed Data Acquisition Figure 1. ADC3214 Functional Block Diagram. www.DataSheet4U.com ADC3214 Specifications1 ANALOG INPUT Input Range ±1.25V, ±2.5V Input Bias Current 5 nA Max. S/H Input Capacitance 10 pF Typ. S/H Input Resistance 100 MΩ Min. A/D Input Resistance 1.25 kΩ to Ground DIGITAL INPUTS Compatibility CMOS, TTL Logic Levels Logic “0” –0.5V Min., 0.8V Max. Logic “1” 2.0V Min., 5.5V Max. Trigger Negative Edge Triggered Loading 1 TTL Load Pulse Width 210 ns Min., 390 ns Max. Output Enable Active Low; B1-B14, O/U Flow Propagation Delay 50 ns Max. DIGITAL OUTPUTS Maximum Output Drive ±2 mA Min. Logic Levels Logic “0” 0V Min., +0.4V Max. Logic “1” +3.5V Min., 5.0V Max. Output Coding Parallel Data, Offset Binary EOC Falling Edge, data valid 20 ns prior to falling edge Over/Under Flow Active High; 1/2 code below FS INTERNAL REFERENCE Voltage 10.0V Typ. Stability ±15 ppm/°C Typ. Available Current2 1 mA Max. DYNAMIC CHARACTERISTICS Maximum Throughput Rate 1 MHz Min. A/D Conversion Time 600 ns Max. S/H Aperture Delay 10 ns Typ. S/H Aperture Jitter 15 ps RMS Typ., 30 ps RMS Max. S/H Feedthrough3 –84 dB Typ., –80 dB Max. Full Power Bandwidth 1.5 MHz Min., 2.5 MHz Typ. Small Signal Bandwidth 3.5 MHz Typ. Signal to Noise Ratio4 76 dB Min., 78 dB Typ. Peak Distortion5 10 kHz –86 dB Max., –95 dB Typ. 100 kHz –82 dB Max., –89 dB Typ. 540 kHz –76 dB Typ. Total Harmonic Distortion6 10 kHz –84 dB Max. 100 kHz –80 dB Max. 540 kHz –74 dB Typ. Step Response7 400 ns to ±0.01% 500 ns to ±0.006% TRANSFER CHARACTERISTICS Resolution 14 bits Quantization Error ±0.5 LSB Relative Accuracy ±0.006% FSR Max. Differential Non-Linearity ±0.75 LSB @ 25°C, ±1 LSB from 0°C to 60°C Monotonicity Guaranteed No Missing Codes Guaranteed from 0°C to 60°C Offset Error8 ±5 mV Max. Gain Error8 ±0.1% FSR Max. Noise9 180 µV RMS Typ., 266 µV RMS Max. STABILITY (0°C TO 60°C) Differential Non-Linearity ±1 ppm FSR/°C Max. Offset Voltage ±100 µV/°C Max. Gain ±25 ppm FSR/°C Max. Warm-Up Time 10 minutes ±15V Supply Rejection ±15 ppm FSR/% change Max. Offset ±15 ppm FSR/% Change Max. Gain ±15 ppm FSR/% Change Max. +5V Supply Rejection Offset ±60 ppm FSR/% Change Max. Gain ±60 ppm FSR/% Change Max. POWER REQUIREMENTS10 ±15V Supplies 14.25V Min., 15.75V Max. +5V Supply +4.75V Min., +5.25V Max. +15V Current Drain 48 mA Typ. –15V Current Drain 63 mA Typ. +5V Current Drain 132 mA Typ. Power Consumption 2.35W Typ. ENVIRONMENTAL & MECHANICAL Temperature Range Rated Performance 0°C to 60°C Storage –25°C to 75°C Relative Humidity (Non-condensing) 0 to 85% to 60°C Dimensions 1.99” x 2.99” x 0.44” (50.5 x 75.9 x 11.2 mm) Shielding Electromagnetic 5 sides Case Potential Ground www.DataSheet4U.com NOTES 1. Unless otherwise noted, all specifications apply at 25°C ambient with power supplies of ±15V and ±5V. 2. External Reference Load to remain stable during conversion. 3. Measured with a full scale step input with a 20V/µs slew rate. 4. Signal-to-noise ratio represents the ratio between the RMS value of the signal and the total RMS noise below the Nyquist rate. The total RMS noise is computed by: (1) summing the noise power in all frequency bins not correlated with the test signal; (2) estimating the total noise power contained in all harmonic frequency bins; and (3) computing the RMS noise from the sum of (1) and (2). 5. Peak distortion represents the ratio between the highest spurious frequency component below the Nyquist rate and the signal. Note that in computing peak distortion the estimated noise allocated to the harmonic frequency bins in computing SNR is first removed. See Note 4. 6. Total harmonic distortion represents the ratio between the RMS sum of all harmonics up to the 100th harmonic and the RMS value of the signal. Note that in computing total harmonic distortion, the estimated noise allocated to the harmonic frequency bins in computing SNR is first removed. See Note 4. 7. Step Response represents the time required to achieve the specified accuracies after a full scale step change at the signal input, specified at a 1 MHz throughput rate. 8. Externally adjustable to zero. See coding and trim procedure. 9. Thermal noise from the S/H and A/D converter, not including quantization noise. 10. Analogic highly recommends the use of linear power supplies with its high performance, high resolution A/D converters. However, if system requirements provide only a +5V supply and limited space, the use of the Analogic SP7015 DC-to-DC converter will provide a low noise solution which will not degrade the ADC3214 performance. ADC3214 SPECIFICATIONS Coding and Trim Procedure Refer to Figures 2 and 3 for the ADC3214 Coding and Trim Procedure. Figure 2 shows the external Offset and Gain Adjust configuration. Figure 3 shows the output Offset Binary coding of the ADC3214 A/D converter. The voltages mentioned in the following Trim Procedure refer to the ±2.5V input range with the numbers in parentheses referring to the ±1.25V input range. Offset Adjustment 1 3 –15V +15V 2 4 6 7 Ext. Off. Adj. 10 kΩ Gain Adjustment Ana. Rtn. Ext. Gain Adj. +Ref. Out 50 kΩ Figure 2. External Offset and Gain Adjust Configuration. To trim the offset of the ADC3214, apply –153 µV (–76 µV) to the analog input. Adjust the external offset trim potentiometer such that each of the 14 bits alternates equally between “0” and “1”. Using the setup as described in Figure 2, the sensitivity of the offset adjustment is typically 6 LSBs per volt. To trim the gain of the ADC3214, apply +2.499542V (+1.249771V) to the analog input and adjust the external gain trim potentiometer such that the 13 MSBs are “1” and the LSB alternates equally between “0” and “1”. Using the setup as described in Figure 2, the sensitivity of the gain adjustment is typically 0.14% per volt. ANALOG INPUT ±1.25V ±2.5V LSB = +1.24985V +2.49970V = 0.00000V 0.00000V = 1.25000V –2.50000V = Pin Label Specifications subject to change without notice. Continued from page 1. Superior performance and ease-of-use make the ADC3214 the ideal solution for applications requiring a sample-and-hold amplifier directly at the input to the A/D converter. Having the S/H amplifier integrated with the A/D converter benefits the system designer in two ways. First, the S/H has been designed specifically to complement the performance of the A/D converter; for example, the acquisition time, hold mode settling and droop rate have been optimized for the A/D converter, resulting in exceptional overall performance. Second, the designer achieves true 14-bit performance, avoiding degradation due to ground loops, signal coupling, jitter and digital noise introduced when separate S/H and A/D convertesr are interconnected. Furthermore, the accuracy, speed, and quality of the ADC3214 are fully ensured by thorough, computer-controlled factory tests of each unit. DIGITAL OUTPUT MSB 11111111111111 10000000000000 00000000000000 B1,B2 . . . . .B14 Figure 3. Output Coding for the ADC3214. Timing Considerations The timing diagram in Figure 4 shows the timing characteristics of the ADC3214 A/D converter. Upon a high-to-low transition of the Trigger input, the internal logic of the ADC3214 places the input S/H amplifier (see Figure 1) into the Hold mode. Approximately 550 ns after Trigger, the internal S/H amplifier returns to the Sample mode to begin acquiring the next sample. www.DataSheet4U.com Trigger S/H Cont. (Int.) EOC N N+1 1 38 0.100" Top View 20 ns 1.800" Typ. 1.990" Max. Data Valid Timing (ns) 0 N–1 N 550 750 1000 0.015" Min. 19 2.990" Max. 20 0.095" Max. 0.440" Max. Figure 4. ADC3214 Timing Diagram. Approximately 200 ns later (750 ns elapsed time), the A/D converter has completed the conversion process and latches the data into the output tri-state latches. The data is valid 20 ns prior