(ADC14DS065 - ADC14DS105) A/D Converter

ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 Dual 14-Bit A/D Converter ADVANCE INFORMATION February 2007 ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 Dual 14-Bit, 65/80/95/105 MSPS A/D Converter with Serial LVDS Outputs General Description NOTE: This is Advance Information for products currently in development. ALL specifications are design targets and are subject to change. The ADC14DS065, ADC14DS080, ADC14DS095, and ADC14DS105 are high-performance CMOS analog-to-digital converters capable of converting two analog input signals into 14-bit digital words at rates up to 65/80/95/105 Mega Samples Per Second (MSPS) respectively. The digital outputs are serialized and provided on differential LVDS signal pairs. These converters use a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1 GHz. The ADC14DS065/080/095/105 may be operated from a single +3.3V power supply. A power-down feature reduces the power consumption to very low levels while still allowing fast wake-up time to full operation. The differential inputs provide a 2V full scale differential input swing. A stable 1.2V internal voltage reference is provided, or the ADC14DS065/080/095/105 can be operated with an external www.DataSheet4U.com 1.2V reference. Output data format (offset binary versus 2's complement) and duty cycle stabilizer are pin-selectable. The duty cycle stabilizer maintains performance over a wide range of clock duty cycles. The ADC14DS065/080/095/105 is available in a 60-lead LLP package and operates over the industrial temperature range of −40°C to +85°C. Features ■ ■ ■ ■ ■ ■ ■ ■ 1 GHz Full Power Bandwidth Internal sample-and-hold circuit and precision reference Low power consumption Clock Duty Cycle Stabilizer Single +3.3V supply operation Offset binary or 2's complement output data format Serial LVDS Outputs 60-pin LLP package, (9x9x0.8mm, 0.5mm pin-pitch) Key Specifications ■ ■ ■ ■ ■ ■ ■ For ADC14DS105 Resolution Conversion Rate SNR (fIN = 240 MHz) SFDR (fIN = 240 MHz) Full Power Bandwidth Power Consumption 14 Bits 105 MSPS 72 dBFS (typ) 83 dBFS (typ) 1 GHz (typ) 1060 mW (typ) Applications ■ ■ ■ ■ ■ High IF Sampling Receivers Wireless Base Station Receivers Test and Measurement Equipment Communications Instrumentation Portable Instrumentation Connection Diagram 20211201 © 2007 National Semiconductor Corporation 202112 www.national.com ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 Block Diagram 20211202 Ordering Information Industrial (−40°C ≤ TA ≤ +85°C) ADC14DS065CISQ ADC14DS080CISQ ADC14DS095CISQ ADC14DS105CISQ Package 60 Pin LLP 60 Pin LLP 60 Pin LLP 60 Pin LLP www.national.com 2 ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 Pin Descriptions and Equivalent Circuits Pin No. ANALOG I/O 3 13 VINA+ VINB+ Differential analog input pins. The differential full-scale input signal level is 2VP-P with each input pin signal centered on a common mode voltage, VCM. Symbol Equivalent Circuit Description 2 14 VINAVINB- 5 11 7 9 VRPA VRPB VCMOA VCMOB VRNA VRNB 6 10 These pins should each be bypassed to AGND with a low ESL (equivalent series inductance) 1 µF capacitor placed very close to the pin to minimize stray inductance. An 0201 size 0.1 µF capacitor should be placed between VRP and VRN as close to the pins as possible, and a 1 µF capacitor should be placed in parallel. VRP and VRN should not be loaded. VCMO may be loaded to 1mA for use as a temperature stable 1.5V reference. It is recommended to use VCMO to provide the common mode voltage, VCM, for the differential analog inputs. Reference Voltage. This device provides an internally developed 1.2V reference. When using the internal reference, VREF should be decoupled to AGND with a 0.1 µF and a 1µF, low equivalent series inductance (ESL) capacitor. This pin may be driven with an external 1.2V reference voltage. This pin should not be used to source or sink current. LVDS Driver Bias Resistor is applied from this pin to Analog Ground. The nominal value is 3.6KΩ The clock input pin. The analog inputs are sampled on the rising edge of the clock input. 59 VREF 29 DIGITAL I/O 18 LVDS_Bias CLK 28 Reset_DLL Reset_DLL input. This pin is normally low. If the input clock frequency is changed abruptly, the internal timing circuits may become unlocked. Cycle this pin high for 1 microsecond to re-lock the DLL. The DLL will lock in several microseconds after Reset_DLL is asserted. 19 OF/DCS This is a four-state pin controlling the input clock mode and output data format. OF/DCS = VA, output data format is 2's complement without duty cycle stabilization applied to the input clock OF/DCS = AGND, output data format is offset binary, without duty cycle stabilization applied to the input clock. OF/DCS = (2/3)*VA, output data is 2's complement with duty cycle stabilization applied to the input clock OF/DCS = (1/3)*VA, output data is offset binary with duty cycle stabilization applied to the input clock. 3 www.national.com ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 Pin No. 57 20 Symbol PD_A PD_B Equivalent Circuit Description This is a two-state input controlling Power Down. PD = VA, Power Down is enabled and power dissipation is reduced. PD = AGND, Normal operation. Test Mode. When this signal is asserted high, a fixed test pattern (10100110001110 msb->lsb) is sourced at the data outputs With this signal deasserted low, the device is in normal operation mode. Note: This signal has no effect when SPI_EN is high and the SPI interface is enabled. Word Alignment Mode. In single-lane mode this pin must be set to logic-0. In dual-lane mode only, when this signal is at logic-0 the serial data words are offset by half-word. With this signal at logic-1 the serial data words are aligned with each other. Note: This signal has no effect when SPI_EN is high and the SPI interface is enabled. Dual-Lane Configuration. The dual-lane mode is selected when this signal is at logic-0. With this signal at logic-1, all data is sourced on a single lane (SD1_x) for each channel. Note: This signal has no effect when SPI_EN is high and the SPI interface is enabled. Serial Clock. This pair of differential LVDS signals provides the serial clock that is synchronous with the Serial Data outputs. A bit of serial data is provided on each of the active serial data outputs with each falling and rising edge of this clock. The user has the ability to set the position of the clock edges at either the data-bitcell boundries (0-degree phase) or at the center of the data-bit-cell boundries (180-degree phase). This differential output is always enabled while the device is powered up. In power-down mode this output is held in logic-low state. A 100-ohm termination resistor must always be used between this pair of signals at the far end of the transmission line. Serial Data Frame. This pair of differential LVDS signals transitions at the serial data word boundries. The SD1_A+/- and SD1_B+/output words always begin with the rising edge of the Frame signal. The falling edge of the Frame signal defines the start of the serial data word presented on the SD0_A+/- and SD0_B+/- signal pairs in the Dual-Lane mode. This differential output is always enabled while the device is powered up. In power-down mode this output is held in logic-low state. A 100-ohm termination resistor must always be used between this pair of signals at the far end of the transmission line. 27 TEST 47 WAM 48 DLC 45 44 OUTCLK+ OUTCLK- 43 42 FRAME+ FRAME- www.national.com 4 ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105 Pin No. Symbol Equivalent Circuit Description Serial Data Output 1 for Channel A. This is a differential LVDS pair of signals that carries channel A ADC’s output in serialized form. The serial data is provided synchronous with the OUTCLK output. In Single-Lane mode each sample’s output is provided in succession. In Dual-Lane mode every other sample output is provided on this output. This differential output is always enabled while the device is powered up. In power-down mode this output holds the last logic state. A 100-ohm termination resistor must always be used between this pair of signals at the far end of the transmission line. Serial Data Output 1 for Channel B. This is a differential LVDS pair of signals that carries channel B ADC’s output in serialized form. The serial data is provided synchronous with the OUTCLK output. In Single-Lane mode each sample’s output is provided in succession. In Dual-Lane mode every other sample output is provided on this output. This differential output is always enabled while the device is powered up. In power-down mode this output holds the last logic state. A 100-ohm termination resistor must always be used between this pair of signals at the far end of the transmission line. Serial Data Output 0 for Channel A. This is a differential LVDS pair of signals that carries channel A ADC’s alternating samples’ output in serialized form in Dual-Lane mode. The serial data is provided synchronous with the OUTCLK output. In Single-Lane mode this differential output is held in high impedance state. This differential output is always enabled while the device is powered up. In powerdown mode this output holds the last logic state. A 100-ohm termination resistor must always be used between this pair of signals at the far end of the transmission line. Serial Data Output 0 for Channel B. This is a differential LVDS pair of signals that carries channel B ADC’s alternating samples’ output in serialized form in Dual-Lane mode. The serial data is provided synchronous with the OUTCLK output. In Single-Lane mode this differential output is held in high impedance state. This differential output is always ena