12-Bit CCD Signal Processor

12-Bit CCD Signal Processor with Precision Timing Core AD9949 FEATURES New AD9949A supports CCD line length > 4096 pixels Correlated double sampler (CDS) 0 dB to 18 dB pixel gain amplifier (PxGA®) 6 dB to 42 dB 10-bit variable gain amplifier (VGA) 12-bit, 36 MSPS analog-to-digital converter (ADC) Black level clamp with variable level control Complete on-chip timing driver Precision Timing™ core with < 600 ps resolution On-chip 3 V horizontal and RG drivers 40-lead LFCSP package GENERAL DESCRIPTION The AD9949 is a highly integrated CCD signal processor for digital still camera applications. Specified at pixel rates of up to 36 MHz, the AD9949 consists of a complete analog front end with A/D conversion, combined with a programmable timing driver. The Precision Timing core allows adjustment of high speed clocks with < 600 ps resolution. The analog front end includes black level clamping, CDS, PxGA, VGA, and a 36 MSPS, 12-bit ADC. The timing driver provides the high speed CCD clock drivers for RG and H1 to H4. Operation is programmed using a 3-wire serial interface. Packaged in a space-saving, 40-lead LFCSP package, the AD9949 is specified over an operating temperature range of −20°C to +85°C. APPLICATIONS Digital still cameras High speed digital imaging applications FUNCTIONAL BLOCK DIAGRAM REFT REFB 0dB TO 18dB CCDIN CDS PxGA 6dB TO 42dB VGA VREF 12-BIT ADC 12 DOUT CLAMP INTERNAL CLOCKS HBLK CLP/PBLK RG H1 TO H4 4 HORIZONTAL DRIVERS PRECISION TIMING CORE CLI AD9949 SYNC GENERATOR INTERNAL REGISTERS 03751-001 HD VD SL SCK SDATA Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. AD9949 TABLE OF CONTENTS Specifications..................................................................................... 3 General Specifications ................................................................. 3 Digital Specifications ................................................................... 3 Analog Specifications................................................................... 4 Timing Specifications .................................................................. 5 Absolute Maximum Ratings............................................................ 6 Thermal Characteristics .............................................................. 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Terminology ...................................................................................... 8 Equivalent Input/Output Circuits .................................................. 9 Typical Performance Characteristics ........................................... 10 System Overview ............................................................................ 11 H-Counter Behavior .................................................................. 11 Serial Interface Timing .................................................................. 12 Complete Register Listing ............................................................. 13 Precision Timing High Speed Timing Generation...................... 18 Timing Resolution...................................................................... 18 High Speed Clock Programmability ........................................ 18 H-Driver and RG Outputs ........................................................ 19 Digital Data Outputs.................................................................. 19 Horizontal Clamping and Blanking ............................................. 21 Individual CLPOB and PBLK Sequences................................ 21 Individual HBLK Sequences..................................................... 21 Generating Special HBLK Patterns .............................................. 23 Horizontal Sequence Control ................................................... 23 External HBLK Signal................................................................ 23 H-Counter Synchronization ..................................................... 24 Power-Up Procedure...................................................................... 25 Recommended Power-Up Sequence ....................................... 25 Analog Front End Description and Operation .......................... 26 DC Restore .................................................................................. 26 Correlated Double Sampler ...................................................... 26 PxGA............................................................................................ 26 Variable Gain Amplifier ............................................................ 29 ADC ............................................................................................. 29 Optical Black Clamp .................................................................. 29 Digital Data Outputs.................................................................. 29 Applications Information .............................................................. 30 Circuit Configuration ................................................................ 30 Grounding and Decoupling Recommendations.................... 30 Driving the CLI Input................................................................ 31 Horizontal Timing Sequence Example.................................... 31 Outline Dimensions ....................................................................... 34 Ordering Guide .......................................................................... 34 REVISION HISTORY 11/04—Data Sheet Changed from Rev. A to Rev. B Changes to Ordering Guide .......................................................... 35 9/04—Data Sheet Changed from Rev. 0 to Rev. A Changes to Features.......................................................................... 1 Changes to Analog Specifications .................................................. 4 Changes to Terminology Section.................................................... 9 Added H-Counter Behavior Section............................................ 12 Changes to Table 7.......................................................................... 14 Changes to Table 12 ....................................................................... 17 Changes to Table 15 ....................................................................... 17 Changes to H-Counter Sync Section ........................................... 24 Changes to Recommended Power-Up Sequence Section ......... 25 Changes to Ordering Guide .......................................................... 35 5/03—Revision 0: Initial Version Rev. B | Page 2 of 36 AD9949 SPECIFICATIONS GENERAL SPECIFICATIONS Table 1. Parameter TEMPERATURE RANGE Operating Storage MAXIMUM CLOCK RATE POWER SUPPLY VOLTAGE AVDD, TCVDD (AFE, Timing Core) HVDD (H1 to H4 Drivers) RGVDD (RG Driver) DRVDD (D0 to D11 Drivers) DVDD (All Other Digital) POWER DISSIPATION 36 MHz, HVDD = RGVDD = 3 V, 100 pF H1 to H4 Loading1 Total Shutdown Mode Min −20 −65 36 2.7 2.7 2.7 2.7 2.7 3.0 3.0 3.0 3.0 3.0 320 1 Typ Max +85 +150 Unit °C °C MHz V V V V V mW mW 3.6 3.6 3.6 3.6 3.6 1 The total power dissipated by the HVDD supply may be approximated using the equation Total HVDD Power = (CLOAD x HVDD x Pixel Frequency) x HVDD x (Number of H – Outputs Used) Reducing the H-loading, using only two of the outputs, and/or using a lower HVDD supply, reduces the power dissipation. DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD = DVDD = DRVDD = HVDD = RGVDD = 2.7 V, CL = 20 pF, unless otherwise noted. Table 2. Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS High Level Output Voltage, IOH = 2 mA Low Level Output Voltage, IOL = 2 mA CLI INPUT High Level Input Voltage (TCVDD/2 + 0.5 V) Low Level Input Voltage RG AND H-DRIVER OUTPUTS High Level Output Voltage (RGVDD – 0.5 V and HVDD – 0.5 V) Low Level Output Voltage Maximum Output Current (Programmable) Maximum Load Capacitance Symbol VIH VIL IIH IIL CIN VOH VOL Min 2.1 0.6 10 10 10 2.2 0.5 Typ Max Unit V V µA µA pF V V VIH–CLI VIL–CLI 1.85 0.85 V V VOH VOL 2.2 0.5 30 100 V V mA pF Rev. B | Page 3 of 36 AD9949 ANALOG SPECIFICATIONS TMIN to TMAX, AVDD = DVDD = 3.0 V, fCLI = 36 MHz, typical timing specifications, unless otherwise noted. Table 3. Parameter CDS Gain Allowable CCD Reset Transient1 Maximum Input Range before Saturation1 Maximum CCD Black Pixel Amplitude1 PIXEL GAIN AMPLIFIER (P×GA) Gain Control Resolution Gain Monotonicity Minimum Gain Maximum Gain VARIABLE GAIN AMPLIFIER (VGA) Maximum Input Range Maximum Output Range Gain Control Resolution Gain Monotonicity Gain Range Minimum Gain (VGA Code 0) Maximum Gain (VGA Code 1023) BLACK LEVEL CLAMP Clamp Level Resolution Clamp Level Minimum Clamp Level (0) Maximum Clamp Level (255) A/D CONVERTER Resolution Differential Nonlinearity (DNL) No Missing Codes Integral Nonlinearity (INL) Full-Scale Input Voltage VOLTAGE REFERENCE Reference Top Voltage (REFT) Reference Bottom Voltage (REFB) SYSTEM PERFORMANCE VGA Gain Accuracy Minimum Gain (Code 0) Maximum Gain (Code 1023) Peak Nonlinearity, 500 mV Input Signal Total Output Noise Power Supply Rejection (PSR) Min Typ 0 500 1.0 ±50 256 0 18 1.0 2.0 1024 Guaranteed 6 42 25