12-Bit Broadband Modem Mixed Signal Front End

Broadband Modem Mixed Signal Front End AD9866 FEATURES Low cost 3.3 V CMOS MxFETM for broadband modems 12-bit D/A converter 2×/4× interpolation filter 200 MSPS DAC update rate Integrated 23 dBm line driver with 19.5 dB gain control 12-bit, 80 MSPS A/D converter −12 dB to +48 dB low noise RxPGA (< 2.5 nV/rtHz) Third order programmable low-pass filter Flexible digital data path interface Half- and full-duplex operation Backward compatible with AD9975 and AD9876 Various power-down/reduction modes Internal clock multiplier (PLL) 2 auxiliary programmable clock outputs Available in 64-lead chip scale package or bare die FUNCTIONAL BLOCK DIAGRAM IOUT_P+ IOUT_P– AD9866 PWR DWN MODE TXEN/SYNC TXCLK ADIO[11:6]/ Tx[5:0] 12 2-4X TxDAC IAMP 0 TO –12dB IOUT_G+ IOUT_N+ IOUT_N– IOUT_G– 0 TO –7.5dB CLK SYN. CLKOUT_1 CLKOUT_2 CLK MULTIPLIER 2M OSCIN XTAL ADIO[5:0]/ Rx[5:0] 12 RXE/SYNC RXCLK AGC[5:0] SPI 6 4 REGISTER CONTROL 0 TO 6dB ∆ = 1dB – 6 TO 18dB –6 TO 24dB ∆ = 6dB ∆ = 6dB 04560-0-001 ADC 80MSPS RX+ 2-POLE LPF 1-POLE LPF RX– APPLICATIONS Powerline networking VDSL and HPNA Figure 1. GENERAL DESCRIPTION www.DataSheet4U.com The AD9866 is a mixed-signal front end (MxFE) IC for transceiver applications requiring Tx and Rx path functionality with data rates up to 80 MSPS. Its flexible digital interface, power saving modes, and high Tx-to-Rx isolation make it well suited for half- and full-duplex applications. The digital interface is extremely flexible allowing simple interfaces to digital back ends that support half- or full-duplex data transfers, thus often allowing the AD9866 to replace discrete ADC and DAC solutions. Power saving modes include the ability to reduce power consumption of individual functional blocks or to power down unused blocks in half-duplex applications. A serial port interface (SPI®) allows software programming of the various functional blocks. An on-chip PLL clock multiplier and synthesizer provide all the required internal clocks, as well as two external clocks from a single crystal or clock source. The Tx signal path consists of a bypassable 2×/4× low-pass interpolation filter, a 12-bit TxDAC, and a line driver. The transmit path signal bandwidth can be as high as 34 MHz at an input data rate of 80 MSPS. The TxDAC provides differential current outputs that can be steered directly to an external load or to an internal low distortion current amplifier. The current amplifier (IAMP) can be configured as a current or voltage mode line driver (with two external npn transistors) capable of delivering in excess of 23 dBm peak signal power. Tx power can be digitally controlled over a 19.5 dB range in 0.5 dB steps. The receive path consists of a programmable amplifier (RxPGA), a tunable low pass filter (LPF), and a 12-bit ADC. The low noise RxPGA has a programmable gain range of −12 dB to +48 dB in 1 dB steps. Its input referred noise is less than 3.3 nV/rtHz for gain settings beyond 30 dB. The receive path LPF cutoff frequency can either be set over a 15 MHz to 35 MHz range or simply bypassed. The 12-bit ADC achieves excellent dynamic performance over a 5 MSPS to 80 MSPS span. Both the RxPGA and the ADC offer scalable power consumption allowing power/performance optimization. The AD9866 provides a highly integrated solution for many broadband modems. It is available in a space-saving 64-lead chip scale package and is specified over the commercial (−40°C to +85°C) temperature range. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. AD9866 TABLE OF CONTENTS Specifications..................................................................................... 3 Tx Path Specifications.................................................................. 3 Rx Path Specifications.................................................................. 4 Power Supply Specifications ....................................................... 5 Digital Specifications ................................................................... 6 Serial Port Timing Specifications............................................... 7 Half-Duplex Data Interface (ADIO Port) Timing Specifications ................................................................................ 7 Full-Duplex Data Interface (Tx and Rx PORT) Timing Specifications ................................................................................ 8 Absolute Maximum Ratings............................................................ 9 Thermal Characteristics .............................................................. 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Typical Performance Characteristics ........................................... 12 Rx Path Typical Performance Characteristics ........................ 12 TxDAC Path Typical Performance Characteristics ............... 16 IAMP Path Typical Performance Characteristics .................. 18 Serial Port ........................................................................................ 19 Register Map Description ......................................................... 21 Serial Port Interface (SPI) ......................................................... 21 Digital Interface .............................................................................. 23 Half-Duplex Mode ..................................................................... 23 Full-Duplex Mode ...................................................................... 24 RxPGA Control .......................................................................... 25 TxPGA Control .......................................................................... 27 Transmit Path .................................................................................. 28 Digital Interpolation Filters ...................................................... 28 TxDAC and IAMP Architecture............................................... 28 Tx Programmable Gain Control .............................................. 30 TxDAC Output Operation........................................................ 30 IAMP Current Mode Operation .............................................. 30 IAMP Voltage Mode Operation ............................................... 31 IAMP Current Consumption Considerations........................ 32 Receive Path .................................................................................... 33 Rx Programmable Gain Amplifier........................................... 33 Low-Pass Filter ........................................................................... 34 Analog to Digital Converter (ADC)........................................ 35 AGC Timing Considerations.................................................... 36 Clock Synthesizer ........................................................................... 37 Power Control and Dissipation .................................................... 39 Power-Down ............................................................................... 39 Half-Duplex Power Savings ...................................................... 39 Power Reduction Options......................................................... 40 Power Dissipation ...................................................................... 42 Mode Select upon Power-Up and Reset.................................. 42 Analog and Digital Loop-back Test Modes ............................ 43 PCB Design Considerations.......................................................... 44 Component Placement.............................................................. 44 Power Planes and Decoupling .................................................. 44 Ground Planes ............................................................................ 44 Signal Routing ............................................................................ 44 Evaluation Board ............................................................................ 46 Outline Dimensions ....................................................................... 47 Ordering Guide .......................................................................... 47 REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 2 of 48 AD9866 SPECIFICATIONS TX PATH SPECIFICATIONS Table 1. AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%; fOSCIN = 50 MHz, fDAC = 200 MHz, RSET = 2.0 kΩ, unless otherwise noted Parameter TxDAC DC CHARACTERISTICS Resolution Update Rate Full-Scale Output Current (IOUTP_FS) Gain Error1 Offset Error Voltage Compliance Range TxDAC GAIN CONTROL CHARACTERISTICS Minimum Gain Maximum Gain Gain Step Size Gain Step Accuracy Gain Range Error TxDAC AC CHARACTERISTICS2 Fundamental Signal-to-Noise and Distortion Signal-to-Noise Ratio THD SFDR IAMP DC CHARACTERISTICS IOUTN Full-Scale Current = IOUTN+ + IOUTN− IOUTG Full-Scale Current = IOUTG+ + IOUTG− AC Voltage Compliance Range IAMPN AC CHARACTERISTICS3 Fundamental IOUTN SFDR (Third Harmonic) IAMP GAIN CONTROL CHARACTERISTICS Minimum Gain Maximum Gain Gain Step Size Gain Step Accuracy IOUTN Gain Range Error REFERENCE Internal Reference Voltage4 Reference Error Reference Drift Tx DIGITAL FILTER CHARACTERISTICS (2× INTERPOLATION) Latency (Relative to 1/ FDAC) −0.2 dB Bandwi