+3 V/+5 V/ Rail-to-Rail Quad/ 8-Bit DAC

a FEATURES Four 8-Bit DACs in One Package +3 V, +5 V and 5 V Operation Rail-to-Rail REF-Input to Voltage Output Swing 2.6 MHz Reference Multiplying Bandwidth Compact 1.1 mm Height TSSOP 16-/20-Lead Package Internal Power ON Reset SPI Serial Interface Compatible—AD7304 Fast Parallel Interface—AD7305 40 A Power Shutdown APPLICATIONS Automotive Output Span Voltage Instrumentation, Digitally Controlled Calibration Pin-Compatible AD7226 Replacement when V DD < 5.5 V VDD PWR ON RESET +3 V/+5 V, Rail-to-Rail Quad, 8-Bit DAC AD7304/AD7305* FUNCTIONAL BLOCK DIAGRAMS VREFB VREFA INPUT 8 REG A 8 INPUT 8 REG B CS SDI/SHDN CLK SERIAL REG INPUT 8 REG C INPUT 8 REG D DAC B 8 REG DAC C 8 REG DAC D 8 REG DAC B VOUTB DAC A REG 8 DAC A VOUTA DAC C VOUTC DAC D VOUTD AD7304 VSS GND VDD CLR LDAC VREFC VREFD VREF INPUT 8 REG A INPUT 8 REG B INPUT 8 REG C 8 INPUT 8 REG D WR A0/SHDN A1 DECODE DAC D 8 REG DAC D VOUTD DAC A 8 REG DAC B 8 REG DAC C 8 REG GENERAL DESCRIPTION The AD7304/AD7305 are quad, 8-bit DACs that operate from a single +3 V to +5 V supply or ±5 V supplies. The AD7304 has a serial interface, while the AD7305 has a parallel interface. Internal precision buffers swing rail-to-rail. The reference input range includes both supply rails allowing for positive or negative fullscale output voltages. Operation is guaranteed over the supply voltage range of +2.7 V to +5.5 V, consuming less than 9 mW from a +3 V supply. The full-scale voltage output is determined by the external reference input voltage applied. The rail-to-rail VREF input to DAC VOUT allows for a full-scale voltage set equal the positive supply VDD, the negative supply VSS or any value in between. The AD7304’s doubled-buffered serial-data interface offers high speed, three-wire, SPI and microcontroller compatible inputs using data in (SDI), clock (CLK) and chip select (CS) pins. Additionally, an internal power-on reset sets the output to zero scale. The parallel input AD7305 uses a standard address decode along with the WR control line to load data into the input registers. The double buffered architecture allows all four input registers to be preloaded with new values, followed by a LDAC control strobe which copies all the new data into the DAC registers thereby updating the analog output values. When operating from less than +5.5 V, the AD7305 is pin-compatible with the popular industry standard AD7226. PWR ON RESET DB0 DB1 DB2 DB3 DB4 DB5 DB6 DAC A VOUTA VOUTB DAC B DAC C VOUTC AD7305 LDAC VSS GND An internal power ON reset places both parts in the zero-scale state at turn ON. A 40 µA power shutdown (SHDN) feature is activated on both parts by tristating the SDI/SHDN pin on the AD7304, and tristating the A0/SHDN address pin on the AD7305. The AD7304/AD7305 are specified over the extended industrial (–40°C to +85°C), and the automotive (–40°C to +125°C) temperature ranges. AD7304s are available in 16-lead plastic DIP (N-16), and wide-body SOL-16 (R-16) packages. The parallel input AD7305 is available in the 20-lead plastic DIP (N-20), and the SOL-20 (R-20) surface mount package. For ultracompact applications the thin 1.1 mm TSSOP-16 (RU-16) package will be available for the AD7304, while the TSSOP-20 (RU-20) will house the AD7305. *Protected under Patent Number 5684481. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 AD7304/AD7305–SPECIFICATIONS ≤ V Parameter STATIC PERFORMANCE Resolution1 Integral Nonlinearity2 Differential Nonlinearity Zero-Scale Error Full-Scale Voltage Error Full-Scale Tempco3 REFERENCE INPUT VREFIN Range Input Resistance (AD7304) Input Resistance (AD7305) Input Capacitance3 ANALOG OUTPUTS Output Voltage Range Output Current Drive Shutdown Resistance Capacitive Load3 LOGIC INPUTS Logic Input Low Voltage Logic Input High Voltage Input Leakage Current5 Input Capacitance3 AC CHARACTERISTICS3 Output Slew Rate Reference Multiplying Total Harmonic Distortion Settling Time6 Shutdown Recovery Time Time to Shutdown DAC Glitch Digital Feedthrough Feedthrough SUPPLY CHARACTERISTICS Positive Supply Current Negative Supply Current Power Dissipation Power Down Power Supply Sensitivity Symbol N INL DNL VZSE VFSE TCVFS VREFIN RREFIN RREFIN CREFIN VOUT IOUT ROUT CL VIL VIH IIL CIL SR BW THD tS tSDR tSDN Q Q VOUT/VREF IDD ISS PDISS IDD_SD PSS Condition (@ VDD = +3 V or +5 V, VSS = 0 V; or VDD = +5 V and VSS = –5 V, VSS REF ≤ VDD, –40 C < TA < +85 C/+125 C, unless otherwise noted.) 3V 8 ±1 ±1 15 ±4 5 VSS/VDD 28 7.5 5 10% 5 V 8 ±1 ±1 15 ±4 5 VSS/VDD 28 7.5 5 VSS/VDD ±3 120 200 0.8 2.4 ± 10 8 1/3.6 10% 5V 8 ±1 ±1 ± 15 ±4 5 VSS/VDD 28 7.5 5 VSS/VDD ±3 120 200 0.8 2.4 ± 10 8 1/3.6 2.6 0.025 1.0/2 2 15 15 2 –65 6 6 60 40 0.004 10% Units Bits LSB max LSB max mV max LSB max ppm/°C typ4 V min/max kΩ typ kΩ typ pF typ V min/max mA typ kΩ typ pF typ V min V max µA max pF max V/µs min/typ MHz typ % µs typ/max µs max µs typ nVs typ nVs typ dB mA max mA max mW max µA typ %/% Monotonic, All Codes 0 to FFH Data = 00H Data = FFH Code = 55H All DACs at Code = 55H VSS/VDD Code = 80H, ∆VOUT < 1 LSB ±3 DAC Outputs Placed in Shutdown State 120 No Oscillation 200 0.6 2.1 ± 10 8 Code = 00H to FFH to 00H Small Signal, VSS = –5 V VREF = 4 V p-p, VSS = –5 V, f = 1 kHz To ± 0.1% of Full Scale To ± 0.1% of Full Scale 1/2.7 1.1/2 2 15 15 2 1.0/2 2 15 15 2 Code = 00H, VREF =1 V p-p, f = 100 kHz VLOGIC = 0 V or VDD, No Load VSS = –5 V VLOGIC = 0 V or VDD, No Load SDI/SHDN = Floating ∆VDD = ± 10% 6 15 40 0.004 6 30 40 0.004 NOTES 1 One LSB = V REF/256. 2 The first three codes (00 H, 01H, 10H) are excluded from the integral nonlinearity error measurement in single supply operation +3 V or +5 V. 3 These parameters are guaranteed by design and not subject to production testing. 4 Typicals represent average readings measured at +25°C. 5 SDI/SHDN and A0/SHDN pins have 30 µA maximum IIL input leakage current. 6 The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground in single supply operation. Specifications subject to change without notice. 5V VREF = 10V p-p f = 20kHz 5V 0V 0V –5V VOUT = 10V p-p –5V (OUT) (IN) Figure 1. AD7304/AD7305 Rail-to-Rail Reference Input to Output at 20 kHz –2– REV. A AD7304/AD7305 TIMING SPECIFICATIONS +85 C/125 C, unless otherwise noted.) Parameter Symbol 1, 2 (@ VDD = +3 V or +5 V, VSS = 0 V; or VDD = +5 V and VSS = –5 V, VSS ≤ VREF ≤ VDD, –40 C < TA < 3V 10% 5V 10% 5V 10% Units INTERFACE TIMING SPECIFICATIONS AD7304 Only Clock Width High tCH Clock Width Low tCL Data Setup tDS Data Hold tDH Load Pulsewidth tLDW Load Setup tLD1 Load Hold tLD2 Clear Pulsewidth tCLWR Select tCSS Deselect tCSH AD7305 Only Data Setup tDS Data Hold tDH Address Setup tAS Address Hold tAH Write Width tWR Load Pulsewidth tLDW Load Setup tLS Load Hold tLH 70 70 50 30 70 40 40 60 30 60 60 30 60 30 60 60 60 30 55 55 40 20 60 30 30 60 20 40 40 20 40 20 50 50 40 20 55 55 40 20 60 30 30 60 20 40 40 20 40 20 50 50 40 20 ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min NOTES 1 These parameters are guaranteed by design and not subject to production testing. 2 All input control signals are specified with t R = tF = 2 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –8 V VREFX to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD Logic Inputs to GND . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V VOUTX to GND . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . 50 mA Package Power Dissipation . . . . . . . . . . . . . . (TJ MAX–TA)/θJA Thermal Resistance θJA 16-Lead Plastic DIP Package (N-16) . . . . . . . . . . 103°C/W 16-Lead SOIC Package (R-16) . . . . . . . . . . . . . . . 73°C/W TSSOP-16 Package (RU-16) . . . . . . . . . . . . . . . . 180°C/W 20-Lead Plastic DIP Package (N-20) . . . . . . . . . . 120°C/W 20-Lead SOIC Package (R-20) . . . . . . . . . . . . . . . 74°C/W TSSOP-20 Package (RU-20) . . . . . . . . . . . . . . . . 155°C/W Maximum Junction Temperature (TJ MAX) . . . . . . . . . +150°C Operating Temperature Range . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature N-16 and N-20 (Soldering, 10 secs) . . . . . . . . . . . . +300°C R-16, R-20, RU-16, RU-20 (Vapor Phase, 60 secs) . . +215°C R-16, R-20, RU-16, RU-20 (Infrared, 15 secs) . . . . +220°C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Model AD7304BN AD7304BR AD7304YR AD7304BRU AD7305BN AD7305BR AD7305YR AD7305BRU Temperature Range –40°C/+85°C –40°C/+85°C –40°C/+125°C –40°C/+85°C –40°C/+85°C –40°C/+85°C –40°C/+125°C –40°C/+85°C Package Description 16-Lead P-DIP 16-Lead SOIC 16-Lead SOIC TSSOP-16 20-Lead P-DIP 20-Lead SOIC 20-Lea