Class-D Audio Power Amplifier

Preliminary Technical Data FEATURES Integrated Stereo Modulator & Power Stage 0.005% THD+N 101.5dB Dynamic Range PSRR > 65 dB RDS-ON < 0.3 Ω (per transistor) Efficiency > 80% @ 5W/6 Ω EMI Optimized Modulator On-Off-Mute Pop Noise Suppression Short Circuit Protection Over-Temperature Protection Low Cost DMOS Process Class-D Audio Power Amplifier AD1990/AD1992/AD1994/AD1996 GENERAL DESCRIPTION The AD199x is a two channel Bridge Tied Load (BTL) switching audio power amplifier with integrated ∑∆ modulator. The modulator accepts a 1Vrms input signal (maximum power) and generates a switching waveform to drive speakers directly. One of the two modulators can control both output stages providing twice the current for single-channel applications. A digital, microcontroller-compatible interface provides control of reset, mute and PGA gain as well as output signals for thermal and over-current error conditions. The output stage can operate from supply voltages ranging from 8V to 20V. The analog modulator and digital logic operate from a 5V supply. AD1990: 5Wx2 (10Wx1) AD1992: 10Wx2 (20Wx1) AD1994: 25Wx2 (50Wx1) AD1996: 40Wx2 (80Wx1) APPLICATIONS Flat Panel Televisions Automotive Amplifiers PC Audio Systems Mini Components PGA0 PGA1 NFR+ 50 AINR NFL+ NFL- 62 63 www.DataSheet4U.com 53 32 31 60 LEFT CHANNEL PVDD 7,8 4,5,6 NFR51 AINL RIGHT CHANNEL PVDD2 DRIVER HIGH SIDE 41,42 PVDD2 43,44,45 OUTL+ 1,2,3 OUTR+ LEVEL SHIFT + DEAD TIME CONTROL PGND1 PVDD1 OUTL9,10 MODULATOR Σ∆ PGA PGA MODULATOR Σ∆ 11,12,13 DRIVER HIGH SIDE DRIVER LOW SIDE LEVEL SHIFT + DEAD TIME CONTROL DRIVER LOW SIDE PGND2 PVDD2 46,47,48 PGND2 39,40 DRIVER HIGH SIDE DRIVER LOW SIDE PVDD2 36,37,38 OUTRPGND1 PGND2 33,34,35 14,15,16 PGND1 PGND2 REF_FILT AVDD 55 Ø1 VOLTAGE REFERENCE Ø2 Ø1 Ø2 57 56 AGND DVDD DGND 24,25 23,26 TEMPERATURE SENSE & OVER-CURRENT PROTECTION OSCILLATOR MODE CONTROL LOGIC MUTE/ POP CONTROL 27 RST/PW DN Figure 1. Block Diagram Rev. PrA – 1/20/05 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved. DCTRL0 DCTRL1 DCTRL2 ERR0 ERR1 MUTE ERR2 MONO CLKI 28 30 29 19 18 17 49 22 21 20 CLKO AD199x Preliminary Technical Data TABLE OF CONTENTS General Description ........................................................................ 1 AD199x—Specifications.................................................................. 3 test conditions unless otherwise noted...................................... 3 Absolute Maximum Ratings............................................................ 6 Pin Configurations And Functional Descriptions ....................... 7 Typical Performance Characteristics ............................................. 8 Functional Description.................................................................. 10 Device Architecture ................................................................... 10 Amplifier Gain............................................................................ 10 System Design............................................................................. 11 Outline Dimensions ....................................................................... 14 ESD Caution................................................................................ 14 Rev. PrA – 1/20/05 | Page 2 of 16 Preliminary Technical Data AD199X—SPECIFICATIONS TEST CONDITIONS UNLESS OTHERWISE NOTED Supply Voltages AVDD DVDD PVDDX Ambient Temperature Load Impedance Clock Frequency Measurement Bandwidth 5V 5V 12 V 25 °C 6Ω 11.2896 MHz 20 Hz to 20 KHz AD199x Table 1. Performance of both channels is identical Parameter OUTPUT POWER (PO) AD1990 AD1992 AD1994 AD1996 Efficiency RON per High Side Transistor per Low Side Transistor Maximum Current Through OUTx Thermal Warning Active Thermal Shutdown Active Overcurrent Shutdown Active Nominal Input Level Modulation Factor PERFORMANCE SPECIFICATIONS Total Harmonic Distortion (THD+N) Min Typ 4 5 8 10 16 25 25 40 84 0.3 0.2 4 135 150 4 1.0 90 0.005 0.007 0.01 0.02 102 102 -100 60 45 20 ±10 Max Units W W W W W W W W % Ω Ω A °C °C A VRMS % % % % % dB dB dB dB dB kΩ mV Test Conditions/Comments RL = 6Ω, PVDD = 20 V, 1 kHz (FTC) @ <0.01% THD+N @ 10% THD+N (FTC) @ <0.01% THD+N @ 10% THD+N (FTC) @ <0.01% THD+N @ 10% THD+N (FTC) @ <0.01% THD+N @ 10% THD+N (FTC) fIN =1 kHz, PO = 5 W, RL = 6Ω @1A @1A Die temperature Die temperature PGA gain = 0 dB PGA = 0 dB, PO = 5 W PGA = 6 dB, PO = 5 W PGA = 12 dB, PO = 5 W PGA = 18 dB, PO = 5 W -60 dB Input Measured channel input = 0 VRMS, other channel = 1 kHz at 5W 20 Hz - 1 kHz 20 Hz – 20 kHz AINL and AINR analog inputs Signal/Noise Ratio (SNR) Dynamic Range (DNR) Crosstalk Power supply rejection (PSRR) DC SPECIFICATIONS Input Impedance Output DC Offset Voltage Rev. PrA – 1/20/05 | Page 3 of 16 AD199x Preliminary Technical Data Parameter POWER SUPPLIES Supply Voltage AVDD Supply Voltage DVDD Supply Voltage PVDDX Powerdown Current AVDD DVDD PVDDX Mute Current AVDD DVDD PVDD Quiesent Current AVDD DVDD PVDDX Operating Current AVDD DVDD PVDD DIGITAL I/O Input Voltage High Input Voltage Low Output Voltage High Output Voltage Low Leakage Current on Digital Inputs Min 4.5 4.5 6.5 Typ 5 5 8-20 0.1 0.1 19 19 2.7 1.5 20 5.2 3.2 22 5.8 Max 5.5 5.5 22.5 0.5 0.5 25 Units V V V Test Conditions/Comments RST/PDN held low µA µA µA MUTE held low mA mA mA Inputs Grounded, Non-Overlap Time = TBD mA mA mA VIN = 1VRMS, PO = 5 W mA mA A V V V V µA 4 2.0 DVDD-0.8 0.4 10 DVDD 0.8 per FET @ 2 mA @ 2 mA Rev. PrA – 1/20/05 | Page 4 of 16 Preliminary Technical Data AD199x Table 2 DIGITAL TIMING (Guaranteed over -40°C to +85°C, AVDD = DVDD = 5.0V ± 10%, PVDDX =12V ± 10%, Non Overlap Time tNOL = Shortest, See Table 6: Non-Overlap Time Settings) Parameter tPDRP tMPDL tMUTEDLY Min 500 Typ Max 5 1 Units ns µs sec Comments RST/PDN minimum low pulsewidth MUTE asserted to output initial response RST/PDN high to MUTE high delay OUTL+/ O UTR+ OUTL-/ OUTRtNOL t NOL Figure 2. Output Timing MUTE t PST t PST OUTX tMPDL t MPDL Figure 3. Mute Timing RESET MUTE t MUTEDLY Figure 4. Reset to Mute Delay Rev. PrA – 1/20/05 | Page 5 of 16 AD199x ABSOLUTE MAXIMUM RATINGS Table 3. AD199x Absolute Maximum Ratings1 Parameter AVDD, DVDD to AGND, DGND PVDDX to PGND AGND to DGND to PGND AVDD, to DVDD Audio Inputs Operating Temperature Range Storage Temperature Range Maximum Junction Temperature θJC Thermal Impedance (LFCSP) θJC Thermal Impedance (PSOP) Lead Temperature Soldering (10 sec) Vapor Phase (60 sec) Infrared (15 sec) Rating -0.3 V to +6.5 V -0.3 V to +30.0 V2 -0.3 V to +0.3 V -0.5 V to +0.5 V AGND to AVDD –40°C to +85°C –65°C to +150°C 150°C 3°C/W 1°C/W 260°C 215°C 220°C Preliminary Technical Data Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition s above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 1 Including any induced voltage due to inductive load REF_FILT NC 64 PGND1 1 PGND1 2 PGND1 3 OUTL+ 4 OUTL+ 5 OUTL+ 6 PV DD1 PV DD1 PV DD1 7 8 9 63 62 61 60 59 58 57 56 55 54 53 52 51 NFR- 50 NFR+ NFL+ 49 48 PGND2 • PIN 1 IDENTIFIER MONO AV DD AGND AGND NFL- AINL AINR NC NC NC NC 47 PGND2 46 PGND2 45 OUTR+ 44 OUTR+ 43 OUTR+ AD1990/92/94 TOP VIEW (Not to Scale) 42 PV DD2 41 PV DD2 40 PV DD2 39 PV DD2 38 OUTR37 OUTR36 OUTR35 PGND2 34 PGND2 33 PGND2 1990-0002 PV DD1 10 OUTL- 11 OUTL- 12 OUTL- 13 PGND1 14 PGND1 15 PGND1 16 17 ERR2 18 ERR1 19 ERR0 20 DCTRL2 21 DCTRL1 22 DCTRL0 23 DGND 24 DV DD 25 DV DD 26 DGND 27 CLKI 28 CLKO 29 MUTE 30 RST/PDN 31 PGA1 32 PGA0 Figure 5. 64 Lead LFCSP Package Rev. PrA – 1/20/05 | Page 6 of 16 Preliminary Technical Data PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS Table 4. Pin Function Descriptions LFCSP Pin No. 1,2,3 4,5,6 7,8,9,10 11,12,13 14,15,16 17 18 19 20 21 22 23,26 24,25 27 28 29 30 31 32 33,34,35 36,37,38 39,40,41,42 43,44,45 46,47,48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 PSOP Pin No. 3 2 1,36 35 34 33 32 31 Name PGND1 OUTL+ PVDD1 OUTLPGND1 ERR2 ERR1 ERR0 DCTRL2 DCTRL1 DCTRL0 DGND DVDD CLKI CLKO MUTE RST/PDN PGA1 PGA0 PGND2 OUTRPVDD2 OUTR+ PGND2 AGND NFR+ NFRNC AINR NC REF_FILT AGND AVDD NC NC AINL NC NFLNFL+ MONO In/Out Description Negative power supply for high power transistors A2 and B2 Output of high power transistor pair, left channel positive polarity Positive power supply for high power transistors, left channel high-side Output of high power transistor pair, left channel negative polarity Negative power supply for high power transistors, left channel low-side Active low thermal shutdown error output Active low thermal warning error output Active low overcurrent error output Non-overlap time setting MSB Non-overlap time setting Non-overlap time setting LSB Negative power supply for low power digital circuitry Positive power supply for low power digital circuitry Clock input for 256 × fS audio modulator clock Inverted version of CLKI for use with external crystal oscillator Active low mu