Audio Switching Amplifier

Audio Switching Amplifier AD1994 FEATURES Integrated stereo modulator and power stage <0.005% THD + N 105 dB dynamic range (A-weighted) 2 × 25 W output power (6 Ω, 10% THD + N) 1 × 50 W output power (3 Ω, 10% THD + N) RDS-ON < 0.3 Ω (per transistor) PSRR > 65 dB On-off-mute pop noise suppression EMI optimized modulator Short-circuit protection Overtemperature protection Low cost DMOS process GENERAL DESCRIPTION The AD1994 is a 2-channel, bridge tied load (BTL), switching audio power amplifier with integrated Σ-Δ modulator. The modulator accepts a single-ended, analog input signal and converts it to a switching waveform to drive speakers directly. One of the two modulators can control both output stages providing twice the current and almost twice the efficiency for single-channel applications. Both modulators can also control external power devices for arbitrarily high output power. A digital, microprocessor-compatible interface provides control of reset, mute, and PGA gain, as well as feedback signals for thermal and overcurrent error conditions. The output stage can operate over a power supply voltages range of 8 V to 20 V. The analog modulator and digital logic operate from a 5 V supply. APPLICATIONS Advanced televisions Compact multimedia systems Minicomponents FUNCTIONAL BLOCK DIAGRAM www.DataSheet4U.com FEEDBACK NETWORK PVDD NFL+ PGA1 PGA0 AVDD NFL– DVDD AD1994 AINL PGA Σ-Δ MODULATOR A1 A2 OUTL+ MOD_FILT ORDER REDUCER B1 LEVEL SHIFTER AND DEAD TIME CONTROL B2 H-BRIDGE C1 C2 OUTL– AINR PGA Σ-Δ MODULATOR OUTR+ CLKI CLKO OSCILLATOR MODE CONTROL LOGIC AND POP/CLICK SUPPRESSION D1 REF_FILT VOLTAGE REFERENCE D2 OUTR– MUTE RESET NFR– DCTRL2 DCTRL1 AGND DCTRL0 ERR2 ERR1 ERR0 NFR+ PGND FEEDBACK NETWORK 05775-001 Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. AD1994 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 15 Overview...................................................................................... 15 Σ-Δ Modulator............................................................................ 15 MUTE and RESET ..................................................................... 15 Mono Mode................................................................................. 16 Modulator Mode ........................................................................ 16 Gain Structure............................................................................. 16 Power Stage ................................................................................. 17 Clocking....................................................................................... 18 Protection Circuits and Error Reporting ................................ 19 Application Circuits ....................................................................... 20 Outline Dimensions ....................................................................... 21 Ordering Guide .......................................................................... 21 REVISION HISTORY 2/06—Revision 0: Initial Version Rev. 0 | Page 2 of 24 AD1994 SPECIFICATIONS Test conditions, unless otherwise specified. Table 1. Parameter SUPPLY VOLTAGES AVDD DVDD PVDD AMBIENT TEMPERATURE LOAD IMPEDANCE CLOCK FREQUENCY PGA GAIN MEASUREMENT BANDWIDTH Ratings 5V 5V 12 V 25°C 6Ω 12.288 MHz 0 dB 20 Hz to 20 kHz Table 2. Parameter RDS-ON Per High-Side Transistor Per Low-Side Transistor MAXIMUM CURRENT THROUGH OUTx THERMAL WARNING ACTIVE THERMAL SHUTDOWN ACTIVE RESTORE TEMPERATURE AFTER THERMAL SHUTDOWN Min Typ 260 210 5 135 150 120 Max 355 265 Unit mΩ mΩ A °C °C °C Test Conditions/Comments T = 25°C T = 25°C Peak Die temperature Die temperature Die temperature Table 3. Performance Specifications Parameter TOTAL HARMONIC DISTORTION AND NOISE (THD + N) Typ 0.003 0.006 0.01 0.02 105 105 −100 Unit % % % % dB dB dB Test Conditions/Comments PGA = 0 dB, PO = 1 W, 1 kHz PGA = 6 dB, PO = 1 W, 1 kHz PGA = 12 dB, PO = 1 W, 1 kHz PGA = 18 dB, PO = 1 W, 1 kHz 1 kHz, A-weighted, 0 dB referred to 1% THD + N output 1 kHz, A-weighted, −60 dB referred to 1% THD + N output PGA = 0 dB, PO = 5 W, 1 kHz SIGNAL-TO-NOISE RATIO (SNR) DYNAMIC RANGE (DNR) CROSSTALK (LEFT-TO-RIGHT OR RIGHT-TO-LEFT) Table 4. DC Specifications Parameter INPUT IMPEDANCE OUTPUT DC OFFSET Typ 20 ±4 Unit kΩ mV Test Conditions/Comments AINL, AINR input pins Independent of PGA setting Rev. 0 | Page 3 of 24 AD1994 Table 5. Power Supplies Parameter ANALOG SUPPLY, AVDD DIGITAL SUPPLY, DVDD POWER TRANSISTOR SUPPLY, PVDD RESET/POWER-DOWN CURRENT AVDD DVDD PVDD QUIESCENT CURRENT AVDD DVDD PVDD OPERATING CURRENT AVDD DVDD PVDD Min 4.5 4.5 6.5 Typ 5.0 5.0 8 to 20 0.6 7.5 19 20 5.5 30 20 5.5 218 27 7 260 Max 5.5 5.5 22.5 1 11 40 Unit V V V μA μA μA mA mA mA mA mA mA RESET held low 5V 5V 12 V Inputs grounded, nonoverlap = minimum 5V 5V 12 V VIN = 1 V rms, RL = 6 Ω, PO = 1 W 5V 5V 12 V Test Conditions/Comments Table 6. Digital I/O Parameter INPUT LOGIC HIGH INPUT LOGIC LOW OUTPUT LOGIC HIGH OUTPUT LOGIC LOW LEAKAGE CURRENT ON DIGITAL OUTPUTS Min 2.0 2.4 0.4 10 Typ Max 0.8 Unit V V V V μA Test Conditions/Comments @ 4 mA @ 4 mA Table 7. Digital Timing Parameter tMD tUD Typ 10 34 Unit μs μs Test Conditions/Comments Delay after MUTE is asserted until output stops switching Delay after MUTE is deasserted until output starts switching tMD MUTE tUD OUTx Figure 2. Mute and Unmute Delay Timing Rev. 0 | Page 4 of 24 05775-002 AD1994 ABSOLUTE MAXIMUM RATINGS Table 8. Parameter AVDD, DVDD to AGND, DGND PVDDx to PGNDx 1 AGND to DGND to PGNDx AVDD, to DVDD Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Thermal Resistance θJA θJC (at the Exposed Pad Surface) θJB (on JEDEC Standard PCB) 1 Rating −0.3 V to +6.5 V −0.3 V to +30.0 V −0.3 V to +0.3 V −0.5 V to +0.5 V –40°C to +85°C –65°C to +150°C 150°C 19.2°C/W 0.9°C/W 9.7°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Including any induced voltage due to inductive load. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 5 of 24 AD1994 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS MONO_EN NFL+ NFL– NC AINL NC MOD_FILT AVDD AGND REF_FILT NC AINR NC NFR– NFR+ MOD_EN 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PGND1 PGND1 PGND1 OUTL+ OUTL+ OUTL+ PVDD1 PVDD1 PVDD1 PVDD1 OUTL– OUTL– OUTL– PGND1 PGND1 PGND1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR AD1994 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGND2 PGND2 PGND2 OUTR+ OUTR+ OUTR+ PVDD2 PVDD2 PVDD2 PVDD2 OUTR– OUTR– OUTR– PGND2 PGND2 PGND2 ERR2 ERR1 MODL/ERR0 MODR/DCTRL2 DCTRL1 DCTRL0 DGND DVDD DVDD DGND CLKI CLKO MUTE RESET PGA1 PGA0 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NC = NO CONNECT Figure 3. Pin Configuration Table 9. Pin Function Descriptions Pin No. 1, 2, 3 4, 5, 6 7, 8, 9, 10 11, 12, 13 14, 15, 16 17 18 19 20 21 22 23, 26 24, 25 27 28 29 30 31 32 33, 34, 35 36, 37, 38 39, 40, 41, 42 43, 44, 45 46, 47, 48 49 Mnemonic PGND1 OUTL+ PVDD1 OUTL− PGND1 ERR2 ERR1 MODL/ERR0 MODR/DCTRL2 DCTRL1 DCTRL0 DGND DVDD CLKI CLKO MUTE RESET PGA1 PGA0 PGND2 OUTR− PVDD2 OUTR+ PGND2 MOD_EN In/Out O O O O O I/O I I Description Negative Power Supply. Used for the A2 and B2 high power transistors. Output of Transistor Pair A1 and A2. Positive Power Supply. Used for the A1 and B1 high power transistors. Output of Transistor Pair B1 and B2. Negative Power Supply. Used for the A2 and B2 high power transistors. Active Low Thermal Shutdown. Active Low Thermal Warning Error Output. Active Low Overcurrent Error Output/M