High-Side Hot-Swap Hall Effect Based Current Monitor

ACS760ELF-20B 12 V High-Side Hot-Swap Hall Effect Based Current Monitor Features and Benefits ▪ Hall-effect current monitor—no external sense resistor required ▪ Analog output voltage (factory trimmed for gain and offset) proportional to applied current ▪ External high-side FET gate drive ▪ 240V*A Power Fault Protection with user-programmable delay ▪ User programmable Overcurrent Fault Protection with programmable delay ▪ 1.5 mΩ internal conductor resistance ▪ Short Circuit Protection isolates failed supply from output in < 2 μs ▪ Active low Fault indicator output signal ▪ External FET failure detection with active low S1 Short failure indicator output signal ▪ User controlled soft start / hot-swap function ▪ Logic enable input pin ▪ 10.8 to 13.2 V, single-supply operation ▪ 2 kV ESD protection for all pins Description The ACS760 combines Allegro® Hall-effect current sense technology with a hot-swap controller resulting in a more efficient integrated controller for 12 V applications. By eliminating the need for a shunt resistor, the I2R losses in the power path are reduced. When the ACS760 is externally enabled, and the voltage rail is above the internal UVLO threshold, the internal charge pump drives the gate of the external FET. When a fault is detected, the gate is disabled while simultaneously alerting the application that a fault has occurred. The integrated protection in the ACS760 incorporates three levels of fault protection, which includes a Power Fault with user-programmable delay, a user-programmable Overcurrent Fault threshold with programmable delay, and Short Circuit protection, which disables the gate in less then 2 μs. Package: 24 pin QSOP (suffix LF) Additionally, in the event the external high-side FET fails short, the ACS760 detects the S1 Short failure and immediately disables the gate and alerts the host system. Unlike the three protection faults, cycling the EN pin does not reset the S1 Short www.DataSheet4U.com failure. Power to the device must be cycled. Approximate Scale Typical Application Backplane VS_IN RV1 A CIN IP 1 2 3 VS_RET Enable REN CEN 4 5 6 7 VOUT 8 9 RSET CG COCD COPD A B C RV1 is required only for inductive loads. D1 should be a Schottky for inductive loads, to eliminate over-stress of the ACS760. FB– is tied to GND at the point of load. 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 C RS1 3.3 V RFAULT RG RFB CLOAD D1 B S1 VLOAD IP+ IP+ IP+ IP+ IP+ IP+ EN VIOUT ISET CG OCDLY OPDLY IP– IP– IP– ACS760 IP– IP– IP– GATE GND FB– FB+ S1SHORT FAULT 760ELF20B-DS, Rev. 2 ACS760ELF-20B 12 V High-Side Hot-Swap Hall Effect Based Current Monitor Selection Guide Part Number Package Packing* 2500 pieces/reel ACS760ELF-20BTR-T QSOP24 surface mount *Contact Allegro for additional packing options Absolute Maximum Ratings Characteristic Forward Voltage, IPx pins* GATE Drive Output Voltage* FB+ Forward Voltage* EN Forward Voltage* All Other Pins Forward Voltage Reverse DC Voltage, All Pins* Reverse Transient DC Voltage, All Pins* Current Sense Output Current Source Current Sense Output Current Sink Operating Ambient Temperature Maximum Junction Temperature Storage Temperature * With respect to GND. Symbol VCC VGATE VFB+ VEN VIN VR Vr IVIOUT(Source) IVIOUT(Sink) TA TJ(max) Tstg Range E 10 μs pulse Notes Rating 24 32 24 32 8 –0.5 –5 1 1 –40 to 85 165 –65 to 170 Units V V V V V V V mA mA ºC ºC ºC Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 2 ACS760ELF-20B 12 V High-Side Hot-Swap Hall Effect Based Current Monitor Pin-out Diagram IP+ 1 IP+ 2 IP+ 3 IP+ 4 IP+ 5 IP+ 6 EN 7 VIOUT 8 ISET 9 CG 10 OCDLY 11 OPDLY 12 24 IP– 23 IP– 22 IP– 21 IP– 20 IP– 19 IP– 18 GATE 17 GND 16 FB– 15 FB+ 14 S1SHORT 13 FAULT Terminal List Table Number 1-6 7 8 9 Name IP+ EN VIOUT ISET Function Primary sensed current conduction path input; power input pins: connected to VCC Enable pin. Toggling this pin to the low state after a FAULT condition resets the ACS760. Analog current sense output. Output voltage on this pin is proportional to the current flowing from the IP+ pins to the IP– pins. Terminal for RSET resistor. Sets Fault Current Threshold, IPF, via external resistor, RSET, connected between this terminal and GND. Factory trimmed 100 μA current source flows out of this pin. Terminal for CG capacitor. May be used to adjust the turn-on time and soft start control of an external MOSFET, S1. Voltage on this pin limits inrush current through MOSFET S1. Set via external capacitance, CG, connected between this pin and GND. This capacitor is charged by an internal 20 μA current source. Terminal for external capacitor, COCD, Used to adjust delay for overcurrent shutdown, set via the external capactior, COCD, connected between this pin and GND. Terminal for external capacitor, COPD, Used to adjust delay for overpower shutdown, set via the external capactior, COPD, connected between this pin and GND. Active low; output signal for short circuit and 240 V*A overload faults; does not trip for S1 short circuit fault. Active low; output signal for MOSFET S1 failure. Input of positive feedback on output voltage. Used to determine 240 V*A threshold by difference between FB+ and FB– pins. Input of negative feedback on output voltage. Used to determine 240 V*A threshold by difference between FB+ and FB– pins. Pulling the FB– pin to 3.3 V, and the OPDLY pin to GND, disables the 240 V*A power fault, which allows the ACS760 to operate purely in Current Mode. Terminal for ground connection. Terminal for external MOSFET, S1. Provides output voltage to drive S1. Current through S1 is controlled at start-up by external capacitance connected between the CG pin and GND. Primary sensed current conduction path output; power output pins. 10 CG 11 12 13 14 15 16 17 18 19-24 OCDLY OPDLY FAULT S1SHORT FB+ FBGND GATE IP– Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 3 ACS760ELF-20B Functional Block Diagram 12 V High-Side Hot-Swap Hall Effect Based Current Monitor Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 4 ACS760ELF-20B 12 V High-Side Hot-Swap Hall Effect Based Current Monitor OPERATING CHARACTERISTICS valid at VCC = 12 V, TA = 0°C to 85°C, unless otherwise noted Characteristic Symbol Test Conditions GENERAL ELECTRICAL CHARACTERISTICS Linear Sensing Range IP Current flows from IP+ to IP- pins Primary Conductor Resistance RPRIMARY TA = 25°C Supply Voltage VCC Voltage applied to IP+ pins Supply Current ICC VUVLOH VCC rising and CG pin current source turns on, EN pin = high Undervoltage Lockout (UVLO) VUVLOL VCC falling and CG pin current source turns off, EN pin = high tUVLOE Enabling, measured from rising VCC > VUVLOH to VGATE > 1 V UVLO Delay to Chip Enable/ Disable tUVLOD Disabling, from falling VCC < VUVLOL to VGATE < 1 V FB+ to FB– Input Resistance RFB TA = 25°C CURRENT SENSE PERFORMANCE CHARACTERISTICS VIOUT Analog Output Propagation TA = 25°C, IP = 0 →20 A, capacitance from VIOUT to GND tPROP Time = 100 pF VIOUT Analog Output 10-90% Rise TA = 25°C, IP = 0 →20 A, capacitance from VIOUT to GND tr Time = 100 pF –3 dB, Ip = 10 A peak-to-peak, TA = 25°C, no external device VIOUT Analog Signal Bandwidth1 f3dB filter, capacitance from VIOUT to GND = 100 pF TA = 25°C Over full ambient operating temperature range VIOUT Analog Signal Sensitivity Sens TA = 25°C Over full ambient operating temperature range VIOUT Analog Noise Level VNOISE(PP) Mean peak-to-peak, TA = 25°C, 50 kHz external device filter Over full ambient operating temperature range and linear VIOUT Analog Nonlinearity ELIN sensing range TA = 0 to 55°C Zero Current Output Voltage VIOUT(Q) TA = 0 to 85°C VOL TA = 25°C Output Voltage Saturation Limits2 VOH TA = 25°C TA = 25°C, IP = 20 A VIOUT Total Error % of IP ETOT TA = 0 to 85°C, IP = 20 A VIOUT DC Output Resistance RVIOUT IVIOUT = 1 mA CURRENT FAULT PERFORMANCE CHARACTERISTICS Load Power Fault Threshold PF(th) TA = 25°C, measured from FAULT signal to VGATE < 1 V, tPFH 2.2 μF capacitance from OPDLY pin to GND, load step from 17 A to 23 A in 100 ns 240 V*A Fault Signal Delay TA = 25°C, measured from FAULT signal to VGATE < 1 V, tPFL OPDLY pin open, load step from 17 A to 23 A in 100 ns Over full operating ambient temperature range, external 240 V*A Fault Signal Delay Drift ∆tPF capacitor with ±5% tolerance Internal –3 dB Filter Frequency for FB+ fFBFILT TA = 25°C and FB– Pins IP Fault Switchpoint Tolerance3 EPF Percentage error of IPF Measured from FAULT signal to VGATE < 1 V, OCDLY pin tIPFLmax open, load step from 17 A to 45 A in 100 ns 4 IPF Fault Signal Delay Measured from FAULT signal to VGATE < 1 V, 2.2 nF capacitIPFH tance from OCDLY pin to GND, load step from 17 A to 45 A in 100 ns Min. 0 – – – – 7.1 – – – – – – – 63 – 5.275 – – 0.38 0.37 – – – – – 222 – – –15 – –15 – – Typ. – 1.5 12 10 – – 500 – 240 2 5 50 65 – 5.416 – 20 ±0.5 – 0.4 0.25 3.6 ±1.0 – 1 230 425 10 – 50 – 8 425 Max. 55 – 13.2 12 10.5 – 900 2 – – – – – 67 – 5.558 – ±2.0 0.42 0.43 – – – ±3.5 – 238 – 12 15 – 15 12 – Units A mΩ V mA V V μs μs kΩ μs μs kHz mV/A mV/A mV/G mV/G mV % V V V V % % Ω W ms μs % kHz % μs μs Continued on the next page… Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 5 ACS760ELF-20B 12 V High-Side Hot-Swap Hall Effect Based Current Monitor OPERATING CHARACTERISTICS, continued valid at VCC = 12 V, TA = 0°C to 85°C, unless otherwise noted Characteristic Symbol Test Conditions Min. Typ. Max. Units Maximum Short Circuit/Overcurrent ISC 60 110