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積體電路樣品承認書
編號： 日期： 94 年 1 月5 日
客戶： 品名：
台康資訊股份有限公司
A2V64S40DTP-7PP A2V64S40DTP-
樣品生產廠商 :
(PSC)
樣品承認簽章處：
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陳炳戎
#6608
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256Mb SDRAM Specification
A2V56S20BTP A2V56S30BTP A2V56S40BTP
Powerchip Semiconductor Corp.
No.12, Li-Hsin Rd.1, Science-based Industrial Park, Hsin-Chu Taiwan, R.O.C. TEL: 886-3-5795000 FAX: 886-3-5792168
www.DataSheet4U.com
256Mb Synchronous DRAM
A2V56S20 BTP (4-BANK x 16,777,216-WORD x 4-BIT) A2V56S30 BTP (4-BANK x 8,388,608-WORD x 8-BIT) A2V56S40 BTP (4-BANK x 4,194,304-WORD x 16-BIT)
Powerchip Semiconductor Corp.
ORDERING INFORMA TION
Frequency Speed(ns)
Order Part Number
Type Standard Low Power Pb-Free
-6 -7 -75 -6L -7L -75L -G6 -G7 -G75
Low Power Package and Pb-Free
-G6L -G7L -G75L 400mil TSOP-2 400mil TSOP-2 400mil TSOP-2 400mil TSOP-2
166MHz 143MHz 133MHz
6 7 7.5
A2V56S20/30/40 BTP A2V56S20/30/40 BTP A2V56S20/30/40 BTP
125MHz
8
A2V56S20/30/40 BTP
-8
-8L
-G8
-G8L
Type Designation Code
A2 V 56 S 3 0 B TP -7
Access Item -6 : 6ns ( 166MHz/3-3-3) -7 : 7 ns (143MHz/3-3-3) -75 : 7.5ns ( 133MHz/3-3-3) -8 : 8 ns (100MHz/2-2-2) TP : TSOP(II) A : 2nd generation , B:3rd generation 0 : Random Column 2 : x4, 3 : x8, 4: x16 56 :256Mbit V :LVTTL
Package Type Process Generation Function Organization Synchronous DRAM Density Interface PSC DRAM
Nov.2003
Rev.1.1
www.DataSheet4U.com
256Mb Synchronous DRAM
Powerchip Semiconductor Corp.
256Mb Synchronous DRAM
A2V56S20ATP (4-BANK x 16,777,216-WORD x 4-BIT) A2V56S30ATP (4-BANK x 8,388,608-WORD x 8-BIT) A2V56S40ATP (4-BANK x 4,194,304-WORD x 16-BIT)
A2V56S20BTP A2V56S30BTP A2V56S40BTP
DESCRIPTION
(4-BANK x 16,777,216-WORD x 4-BIT) (4-BANK x 8,388,6084-WORD x 8-BIT) (4-BANK x 4,194,304-WORD x 16-BIT)
A2V56S20BTP is organized as 4-bank x 16,777,216-word x 4-bit Synchronous DRAM with LVTTL interface and A2V56S30BTP is organized as 4-bank x 8,388,608-word x 8-bit and A2V56S40BTP is organized as 4-bank x 4,194, 304-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK.
A2V56S20BTP,A2V56S30BTP and A2V56S40BTP achieve very high speed clock rates up to 166MHz, and are suitable for main memories or graphic memories in computer systems.
FEATURES
ITEM
tCLK tRAS tRCD tAC tRC Icc1 Clock Cycle Time (Min.) CL=2 CL=3
-6
6 42 CL=2 CL=3 V56S20 15 5 60 100 110 130 3
A2V56S20/30/40BTP -7E -7 -75 -8
7 7 45 20 5.4 5.4 63 100 110 130 3 7 45 20 5.4 63 100 110 130 3 10 7.5 45 20 6 5.4 67.5 100 110 130 3 10 8 48 20 6 6 70 95 100 120 3
Unit ns ns ns ns ns ns ns mA mA mA mA
Active to Precharge Command Period (Min.) (Min.) Row to Column Delay Access Time from CLK Ref /Active Command Period Operation Current (Single Bank) (Max.) (Min.) (Max.) V56S30 V56S40
Icc6
Self Refresh Current
(Max.) -6,-7E,-7,-75,-8
- Single 3.3V ±0.3V power supply - Max. Clock frequency: -6:166MHz<3-3-3>/-7E:143MHz<2-2-2>/-7:143MHz<3-3-3>/-75:133MHz<3-3-3>/-8:100MHz<2-2-2> - Fully synchronous operation referenced to clock rising edge - 4-bank operation controlled by BA0,BA1(Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8/FP (programmable) - Burst type- Sequential and interleave burst (programmable) - Byte Control- DQML and DQMU (A2V56S40BTP) - Random column access - Auto precharge / All bank precharge controlled by A10 - Auto and self refresh - 8192 refresh cycles /64ms(4 banks concurrent refresh) - LVTTL Interface - Row address A0-12 /Column address A0-9 , 11(x4) / A0-9(x8) / A0-8(x16) - Package 400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
Nov.2003
Page -1
Rev.1.1
www.DataSheet4U.com
256Mb Synchronous DRAM
A2V56S20BTP (4-BANK x 16,777,216-WORD x 4-BIT) A2V56S30BTP (4-BANK x 8,388,608-WORD x 8-BIT) A2V56S40BTP (4-BANK x 4,194,304-WORD x 16-BIT)
Powerchip Semiconductor Corp.
PIN CONFIGURATION (TOP VIEW)
A2V56S20BTP
A2V56S30BTP A2V56S40BTP
Vdd Vdd DQ0 NC VddQ VddQ NC NC DQ1 DQ0 VssQ VssQ NC NC DQ2 NC VddQ VddQ NC NC DQ3 DQ1 VssQ VssQ NC NC Vdd Vdd NC NC /WE /WE /CAS /CAS /RAS /RAS /CS /CS BA0 BA0 BA1 BA1 A10/AP A10/AP A0 A0 A1 A1 A2 A2 A3 A3 Vdd Vdd Vdd DQ0 VddQ DQ1 DQ2 VssQ DQ3 DQ4 VddQ DQ5 DQ6 VssQ DQ7 Vdd DQML /WE /CAS /RAS /CS BA0 BA1 A10/AP A0 A1 A2 A3 Vdd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
Vss DQ15 VssQ DQ14 DQ13 VddQ DQ12 DQ11 VssQ DQ10 DQ9 VddQ DQ8 Vss NC DQMU CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 Vss
Vss DQ7 VssQ NC DQ6 VddQ NC DQ5 VssQ NC DQ4 VddQ NC Vss NC DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 Vss
Vss NC VssQ NC DQ3 VddQ NC NC VssQ NC DQ2 VddQ NC Vss NC DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 Vss
400mil x 875mil 54pin 0.8mm pitch TSOP(II)
CLK CKE /CS /RAS /CAS /WE DQ0-15
: Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Data I/O
DQM, DQMU/L A0-12 BA0,1 Vdd VddQ Vss VssQ
: Output Disable / Write Mask : Address Input : Bank Address Input : Power Supply : Power Supply for Output : Ground : Ground for Output
Nov.2003
Page- 2
Rev.1.1
www.DataSheet4U.com
256Mb Synchronous DRAM
A2V56S20 BTP (4-BANK x 16,777,216-WORD x 4-BIT) A2V56S30 BTP (4-BANK x 8,388,608-WORD x 8-BIT) A2V56S40 BTP (4-BANK x 4,194,304-WORD x 16-BIT)
Powerchip Semiconductor Corp.
BLOCK DIAGRAM
DQ0-7
I/O Buffer
Memory Array
8192x1024x8 Cell Array
Memory Array
8192x1024x8 Cell Array
Memory Array
8192x1024x8 Cell Array
Memory Array
8192x1024x8 Cell Array
Bank #0
Bank #1
Bank #2
Bank #3
Mode Register Control Circuitry
Address Buffer Clock Buffer
Control Signal Buffer
A0-12
BA0,1
CLK
CKE
/CS
/RAS
/CAS
/WE
DQM
Note:This figure shows the A2V56S30BTP The A2V56S20BTP configuration is 8192x2048x4 of cell array and DQ0-3 The A2V56S40BTP configuration is 8192x512x16 of cell array and DQ0-15
Type Designation Code
A2 V 56 S 3 0 B TP
-7
Access Item -6 : 6ns ( 166MHz/3-3-3) -7E : 7 ns (143MHz/2-2-2) -7 : 7 ns (143MHz/3-3-3) -75 : 7.5ns ( 133MHz/3-3-3) -8 : 8 ns (100MHz/2-2-2) TP : TSOP(II) A : 2nd generation, B:3rd generation 0 : Random Column 2 : x4, 3 : x8, 4: x16 56 :256Mbit V :LVTTL
Package Type Process Generation Function Organization Synchronous DRAM Density Interface PSC DRAM
Nov.2003
Page- 3
Rev.1.1
www.DataSheet4U.com
256Mb Synchronous DRAM
A2V56S20BTP (4-BANK x 16,777,216-WORD x 4-BIT) A2V56S30BTP (4-BANK x 8,388,608-WORD x 8-BIT) A2V56S40BTP (4-BANK x 4,194,304-WORD x 16-BIT)
Powerchip Semiconductor Corp.
PIN FUNCTION
CLK
Input
Master Clock: All other inputs are referenced to the rising edge of CLK Clock Enable: CKE controls internal clock.When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / self-refresh. After self-refresh mode is started, CKE becomes asynchronous input. Self-refresh is maintained as long as CKE is low. Chip Select: When /CS is high, any command means No Operation. Combination of /RAS, /CAS, /WE defines basic commands. A0-12 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-12. The Column Address is specified by A0-9,11(x4)/A0-9(x8)/A0-8(x16). A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, all banks are precharged. Bank Address: BA0,1 specifies one of four banks to which a command is applied. BA0,1 must be set with ACT, PRE , READ , WRITE commands.
CKE
Input
/CS /RAS, /CAS, /WE
Input Input
A0-12
Input
BA0,1 DQ0-3(x4), DQ0-7(x8), DQ0-15(x16) DQM(x4,x8), DQMU/L(x16) Vdd, Vss VddQ, VssQ
Input
Input / Output Data In and Data out are referenced to the rising edge of CLK.
Din Mask / Output Disable: When DQM(U/L) is high in burst write, Din for the current cycle is masked. When DQM(U/L) is high in burst read, Dout is disabled at the next but one cycle. Power Supply for the memory array and peripheral circuitry.
Input
Power Supply
Power Supply VddQ and VssQ are supplied to the Output Buffers only.
Nov.2003
Page -4
Rev.1.1
www.DataSheet4U.com
256Mb Synchronous DRAM
A2V56S20BTP (4-BANK x 16,777,216-WORD x 4-BIT) A2V56S30BTP (4-BANK x 8,388,608-WORD x 8-BIT) A2V56S40BTP (4-BANK x 4,194,304-WORD x 16-BIT)
Powerchip Semiconductor Corp.
BASIC FUNCTIONS
The A2V56S20 , 30 and 40 BTP provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh opt ion, and precharge option, respectively . To know the detailed definition of commands, please see the command truth table.
CLK /CS /RAS /CAS /WE CKE A10
Chip Select : L=select, H=deselect Command Command Command Refresh Option @ refresh command Precharge Option @ precharge or read/write command
define basic command
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-precharge, READA).
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write (auto-precharge, WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active
