Description
93LCS56/66 2K/4K 2.5V Microwire® Serial EEPROM with Software Write Protect FEATURES • Single supply with programming operation down to 2.5V • Low power CMOS technology - 1 mA active current typical - 5 µA standby current (typical) at 3.0V • x16 memory organization - 128x16 (93LCS56) - 256x16 (93LCS66) • Software write protection of user defined memory space • Self timed erase and write cycles • Automatic ERAL before WRAL • Power on/off data protection • Industry standard 3-wire serial I/O • Device status signal during E/W • Sequential READ function • 1,000,000 E/W cycles guaranteed • Data retention > 200 years • 8-pin PDIP/SOIC and 14-pin SOIC packages • Temperature ranges supported - Commercial (C): 0˚C to +70˚C - Industrial (I): -40˚C to +85˚C BLOCK DIAGRAM VCC V SS MEMORY ARRAY ADDRESS DECODER ADDRESS COUNTER OUTPUT BUFFER DATA REGISTER DI PRE PE CS MODE DECODE LOGIC DO CLK CLOCK GENERATOR DESCRIPTION The Microchip Technology Inc. 93LCS56/66 are low voltage Serial Electrically Erasable PROMs with memory capacities of 2K bits/4K bits respectively. A write protect register is included in order to provide a user defined region of write protected memory. All memory locations greater than or equal to the address placed in the write protect register will be protected from any attempted write or erase operation. It is also possible to protect the address in the write protect register permanently by using a one time only instruction (PRDS). Any attempt to alter data in a register whose address is equal to or greater than the address stored in the protect register will be aborted. Advanced CMOS technology makes this device ideal for low power non-volatile memory applications. PACKAGE TYPES SOIC NC CS DIP CS CLK DI DO 1 2 3 4 93LCS56 93LCS66 8 7 6 5 VCC PRE PE VSS CS CLK DI DO 1 2 3 4 93LCS56 93LCS66 SOIC 8 7 6 5 VCC PRE PE VSS CLK NC DI DO NC 1 2 3 4 5 6 7 93LCS56 93LCS66 14 13 12 11 10 9 8 NC VCC PRE NC PE VSS NC Microwire is a registered trademark of National Semiconductor Incorporated. © 1996 Microchip Technology Inc. Preliminary This document was created with FrameMaker 4 0 4 DS11181D-page 1 93LCS56/66 1.0 1.1 ELECTRICAL CHARACTERISTICS Maximum Ratings* TABLE 1-1: Name CS CLK DI DO VSS PE PRE VCC PIN FUNCTION TABLE Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Program Enable Protect Register Enable Power Supply VCC...................................................................................7.0V All inputs and outputs w.r.t. VSS ............... -0.6V to VCC +1.0V Storage temperature ..................................... -65˚C to +150˚C Ambient temp. with power applied ................ -65˚C to +125˚C Soldering temperature of leads (10 seconds) ............. +300˚C ESD protection on all pins................................................4 kV *Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-2: DC AND AC ELECTRICAL CHARACTERISTICS VCC = +2.5V to +6.0V Commercial(C): Tamb = 0˚C to +70˚C Industrial (I): Tamb = -40˚C to +85˚C Parameter High level input voltage Low level input voltage Low level output voltage Symbol Min 2.0 -0.3 — — 2.4 VCC-0.2 -10 -10 — — — — — Max VCC +1 0.8 0.4 0.2 — — 10 10 7 3 1 500 100 30 2 1 — — — — — — — — — — — 400 100 Units V V V V V V µA µA pF mA mA µA µA µA MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions VCC ≥ 2.5V VCC ≥ 2.5V IOL = 2.1 mA; VCC = 4.5V IOL = 100 µA; VCC = 2.5V IOH = -400µA; VCC = 4.5V IOH = -100µA; VCC = 2.5V VIN = 0.1V to VCC VOUT = 0.1V to Vcc VIN/VOUT = 0V (Note 1 & 2) Tamb = +25˚C; FCLK = 1 MHz FCLK = 2 MHz; VCC = 3.0V (Note 2) FCLK = 2 MHz; VCC = 6.0V FCLK = 1 MHz; VCC = 3.0V CLK = CS = 0V; VCC = 6.0V CLK = CS = 0V; VCC = 3.0V VCC ≥ 4.5V VCC < 4.5V VIH VIL VOL1 VOL2 High level output voltage VOH1 VOH2 Input leakage current ILI Output leakage current ILO Pin capacitance CIN, COUT (all inputs/outputs) Operating current ICC Write ICC Read Standby current Clock frequency ICCS FCLK Clock high time TCKH 250 Clock low time TCKL 250 Chip select setup time TCSS 50 Chip select hold time TCSH 0 Chip select low time TCSL 250 PRE setup time TPRES 100 PE setup time TPES 100 PRE hold time TPREH 0 PE hold time TPEH 500 Data input setup time TDIS 100 Data input hold time TDIH 100 Data output delay time TPD — Data output disable time TCZ — Note 1: This parameter is tested at Tamb = 25˚C and FCLK = 1 MHz. 2: This parameter is periodically sampled and not 100% tested. Relative to CLK Relative to CLK Relative to CLK Relative to CLK Relative to CLK Relative to CLK Relative to CLK Relative to CLK CL=100 pF CL=100 pF (Note 2) DS11181D-page 2 Preliminary This document was created with FrameMaker 4 0 4 © 1996 Microchip Technology Inc. 93LCS56/66 TABLE 1-2: DC AND AC ELECTRICAL CHARACTERISTICS (Continued) VCC = +2.5V to +6.0V Commercial(C): Tamb = 0˚C to +70˚C Industrial (I): Tamb = -40˚C to +85˚C Parameter Status valid time Program cycle time Symbol TSV TWC TEC TWL — Min Max 500 10 15 30 — Units ns ms ms ms cycles Conditions CL=100 pF ERASE/WRITE mode (Note 3) ERAL mode WRAL mode 25°C, Vcc = 5.0V, Block Mode (Note 4) Endurance 1M 3: Typical program cycle time is 4 ms per word. 4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website. TABLE 1-3: INSTRUCTION SET FOR 93LCS56*/66 93LCS56/66 (x 16 organization) Instruction SB Opcode READ EWEN ERASE 1 1 1 10 00 11 Address A7 - A0 11XXXXXX A7 - A0 Data In — — — Data Out D15-D0 High-Z (RDY/ BSY) (RDY/ BSY) (RDY/ BSY) (RDY/ BSY) High-Z A7-A0 High-Z PRE 0 0 PE X 1 1 Comments Reads data stored in memory, starting at specified address (.Note). Erase/Write Enable must precede all programming modes. Erase data at specified address location if address is unprotected (Note). Erase all registers to “FF”. Valid only when Protect Register is cleared. Writes register if address is unprotected. Writes all registers. Valid only when Protect Register is cleared. Erase/Write Disable deactivates all programming instructions. Reads address stored in Protect Register. Must immediately precede PRCLEAR, PRWRITE and PRDS instructions. Clears the Protect Register such that all data are NOT write-protected. Programs address into Protect Register. Thereafter, memory addresses greater than or equal to the address in Protect Register are write-protected. ONE TIME ONLY instruction after which the address in the Protect Register cannot be altered. ERAL WRITE WRAL EWDS PRREAD PREN 1 1 1 1 1 1 00 01 00 00 10 00 10XXXXXX A7 - A0* 01XXXXXX 00XXXXXX XXXXXXXX 11XXXXXX — D15 - D0 D15 - D0 — — — 0 0 0 0 1 1 1 1 1 X X 1 PRCLEAR PRWRITE 1 1 11 01 11111111 A7 - A0* — — (RDY/ BSY) (RDY/ BSY) 1 1 1 1 PRDS 1 00 00000000 — (RDY/ BSY) 1 1 Note: Address A7 bit is a “don’t care” on 93LCS56. © 1996 Microchip Technology Inc. Preliminary DS11181D-page 3 93LCS56/66 2.0 FUNCTIONAL DESCRIPTION 2.4 READ The 93LCS56/66 is organized as 128/256 registers by 16 bits. Instructions, addresses and write data are clocked into the DI pin on the rising edge of the clock (CLK). The DO pin is normally held in a high-Z state except when reading data from the device, or when checking the ready/busy status during a programming operation. The ready/busy status can be verified during an Erase/Write operation by polling the DO pin; DO low indicates that programming is still in progress, while DO high indicates the device is ready. The DO will enter the high-Z state on the falling edge of the CS. The READ instruction outputs the serial data of the addressed memory location on the DO pin. A dummy zero bit precedes the 16 bit output string. The output data bits will toggle on the rising edge of the CLK and are stable after the specified time delay (TPD). Sequential read is possible when CS is held high. The memory data will automatically cycle to the next register and output sequentially. 2.5 Erase/Write Enable and Disable (EWEN, EWDS) 2.1 START Condition The START bit is detected by the device if CS and DI are both HIGH with respect to the positive edge of CLK for the first time. Before a START condition is detected, CS, CLK, and DI may change in any combination (except to that of a START condition), without resulting in any device operation (READ, WRITE, ERASE, EWEN, EWDS, ERAL, WRAL, PRREAD, PREN, PRCLEAR, PRWRITE, and PRDS). As soon as CS is HIGH, the device is no longer in the standby mode. An instruction following a START condition will only be executed if the required amount of opcode, address and data bits for any particular instruction is clocked in. After execution of an instruction (i.e., clock in or out of the last required address or data bit) CLK and DI become don't care bits until a new start condition is detected. The 93LCS56/66 powers up in the Erase/Write Disable (EWDS) state. All programming modes must be preceded by an Erase/Write Enable (EWEN) instruction. The PE pin MUST be held “high” while loading the EWEN instruction. Once the EWEN instruction is executed, programming remains enabled until an EWDS instruction is executed or VCC is removed from the device. To protect against accidental data disturb, the EWDS instruction can be used to disable all Erase/ Write functions and should follow all programming operations. Execution of a READ instruction is independent of both the EWEN and EWDS instructions. 2.6 ERASE 2.2 DI/DO The ERASE

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