INTEGRATED CIRCUITS
PCA9535 16-bit I2C and SMBus, low power I/O port with interrupt
Product data 2003 Jun 27
Philips Semiconductors
Philips Semiconductors
Product data
16-bit I2C and SMBus, low power I/O port with interrupt
PCA9535
I2C/SMBus applications and was developed to enhance the Philips family of I2C I/O expanders. The improvements include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O configuration, and smaller packaging. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, pushbuttons, LEDs, fans, etc. The PCA9535 consist of two 8-bit Configuration (Input or Output selection); Input, Output and Polarity inversion (Active HIGH or Active LOW operation) registers. The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each Input or Output is kept in the corresponding Input or Output register. The polarity of the read register can be inverted with the Polarity Inversion Register. All registers can be read by the system master. Although pin-to-pin and I2C address compatible with the PCF8575, software changes are required due to the enhancements and are discussed in Application Note AN469. The PCA9535 is identical to the PCA9555 except for the removal of the internal I/O pull-up resistor which greatly reduces power consumption when the I/Os are held LOW. The PCA9535 open-drain interrupt output is activated when any input state differs from its corresponding input port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine. Three hardware pins (A0, A1, A2) vary the fixed I2C address and allow up to eight devices to share the same I2C/SMBus. The fixed I2C address of the PCA9535 is the same as the PCA9554 allowing up to eight of these devices in any combination to share the same I2C/SMBus.
FEATURES
• Operating power supply voltage range of 2.3 V-5.5 V • 5 V tolerant I/Os • Polarity inversion register • Active LOW interrupt output • Low stand-by current • Noise filter on SCL/SDA inputs • No glitch on power-up • Internal power-on reset • 16 I/O pins which default to 16 inputs • 0 to 400 kHz clock frequency • ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V • Latch-up testing is done to JESDEC Standard JESD78 which • Offered in three different packages: SO24, TSSOP24, and
HVQFN24 exceeds 100 mA MM per JESD22-A115, and 1000 V CDM per JESD22-C101
DESCRIPTION
The PCA9535 is a 24-pin CMOS device that provide 16 bits of General Purpose parallel Input/Output (GPIO) expansion for
ORDERING INFORMATION
PACKAGES 24-Pin Plastic SO 24-Pin Plastic TSSOP TEMPERATURE RANGE -40 to +85 °C -40 to +85 °C ORDER CODE PCA9535D PCA9535PW TOPSIDE MARK PCA9535D PCA9535PW DRAWING NUMBER SOT137-1 SOT355-1 SOT616-1
24-Pin Plastic HVQFN -40 to +85 °C PCA9535BS 9535 Standard packing quantities and other packing data are available at www.philipslogic.com/packaging. I2C is a trademark of Philips Semiconductors Corporation. SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I2C patent.
2003 Jun 27
2
Philips Semiconductors
Product data
16-bit I2C and SMBus, low power I/O port with interrupt
PCA9535
PIN CONFIGURATION — SO, TSSOP
INT A1 A2 I/O0.0 I/O0.1 I/O0.2 I/O0.3 I/O0.4 I/O0.5 1 2 3 4 5 6 7 8 9 24 VDD 23 SDA 22 SCL 21 A0 20 I/O1.7 19 I/O1.6 18 I/O1.5 17 I/O1.4 16 I/O1.3
PIN CONFIGURATION —HVQFN
21 VDD 20 SDA 19 SCL 18 A0 17 I/O1.7 16 I/O1.6 15 I/O1.5 14 I/O1.4 13 I/O1.3 I/O1.2 12 I/O1.0 10 I/O1.1 11 7 8 I/O0.7 9 VSS 22 INT 24 A2 I/O0.0 I/O0.1 I/O0.2 I/O0.3 I/O0.4 I/O0.5 1 2 3 4 5 6 I/O0.6 23 A1
I/O0.6 10 I/O0.7 11 VSS 12
15 I/O1.2 14 I/O1.1 13 I/O1.0
TOP VIEW
SU01438 su01683
Figure 1. Pin configuration — SO, TSSOP
Figure 2. Pin configuration — HVQFN
PIN DESCRIPTION
SO, TSSOP PIN NUMBER 1 2 3 4-1 1 12 13-20 21 22 23 24 HVQFN PIN NUMBER 22 23 24 1-8 9 10-17 18 19 20 21 SYMBOL INT A1 A2 I/O0.0-I/O0.7 VSS I/O1.0-I/O1.7 A0 SCL SDA VDD FUNCTION Interrupt output (open drain) Address input 1 Address input 2 I/O0.0 to I/O0.7 Supply ground I/O1.0 to I/O1.7 Address input 0 Serial clock line Serial data line Supply voltage
2003 Jun 27
3
Philips Semiconductors
Product data
16-bit I2C and SMBus, low power I/O port with interrupt
PCA9535
BLOCK DIAGRAM
I/O1.0 I/O1.1 A0 A1 A2 WRITE pulse READ pulse 8-BIT INPUT/ OUTPUT PORTS I/O1.2 I/O1.3 I/O1.4 I/O1.5 I/O1.6 I/O1.7
I2C/SMBUS CONTROL I/O0.0 I/O0.1 SCL SDA I/O0.2 INPUT FILTER 8-BIT INPUT/ OUTPUT PORTS I/O0.3 I/O0.4 I/O0.5 I/O0.6 I/O0.7 VINT VSS POWER-ON RESET LP FILTER INT NOTE: ALL I/Os ARE SET TO INPUTS AT RESET
WRITE pulse READ pulse VDD
SU01439
Figure 3. Block diagram
2003 Jun 27
4
Philips Semiconductors
Product data
16-bit I2C and SMBus, low power I/O port with interrupt
PCA9535
SIMPLIFIED SCHEMATIC OF I/Os
DATA FROM SHIFT REGISTER CONFIGURATION REGISTER DATA FROM SHIFT REGISTER D FF WRITE CONFIGURATION PULSE WRITE PULSE CK Q D FF I/O PIN CK Q Q2 Q Q Q1 OUTPUT PORT REGISTER DATA VDD
OUTPUT PORT REGISTER INPUT PORT REGISTER D FF READ PULSE CK Q Q
VSS
INPUT PORT REGISTER DATA
TO INT
DATA FROM SHIFT REGISTER WRITE POLARITY PULSE
D FF CK
Q
POLARITY REGISTER DATA
Q
POLARITY INVERSION REGISTER SU01682
NOTE:
At Power-on Reset, all registers return to default values. Figure 4. Simplified schematic of I/Os
I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V. If the I/O is configured as an output, then either Q1 or Q2 is on, depending on the state of the Output Port register. Care should be exercised if an external voltage is applied to an I/O configured as an output because of the low impedance path that exists between the pin and either VDD or VSS.
2003 Jun 27
5
Philips Semiconductors
Product data
16-bit I2C and SMBus, low power I/O port with interrupt
PCA9535
REGISTERS Command Byte
Command 0 1 2 3 4 5 6 7 Register Input port 0 Input port 1 Output port 0 Output port 1 Polarity inversion port 0 Polarity inversion port 1 Configuration port 0 Configuration port 1
POWER-ON RESET
When power is applied to VDD, an internal power-on reset holds the PCA9535 in a reset state until VDD has reached VPOR. At that point, the reset condition is released and the PCA9535 registers and SMBus state machine will initialize to their default states.
DEVICE ADDRESS
slave address
0
1
0
0
A2
A1
A0 R/W
fixed
programmable su01441
The command byte is the first byte to follow the address byte during a write transmission. It is used as a pointer to determine which of the following registers will be written or read.
Figure 5. PCA9535 address
BUS TRANSACTIONS Registers 0 and 1 — Input Port Registers
This register is an input-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by Register 3. Writes to this register have no effect.
Writing to the port registers
Data is transmitted to the PCA9535 by sending the device address and setting the least significant bit to a logic 0 (see Figure 5 for device address). The command byte is sent after the address and determines which register will receive the data following the command byte. The eight registers within the PCA9535 are configured to operate as four register pairs. The four pairs are Input Ports, Output Ports, Polarity Inversion Ports, and Configuration Ports. After sending data to one register, the next data byte will be sent to the other register in the pair (see Figures 6 and 7). For example, if the first byte is sent to Output Port (register 3), then the next byte will be stored in Output Port 0 (register 2). There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register may be updated independently of the other registers.
Registers 2 and 3 — Output Port Registers
bit
default O0.7 1 O1.7 1 O0.6 1 O1.6 1 O0.5 1 O1.5 1 O0.4 1 O1.4 1 O0.3 1 O1.3 1 O0.2 1 O1.2 1 O0.1 1 O1.1 1 O0.0 1 O1.0 1
bit
default
This register is an output-only port. It reflects the outgoing logic levels of the pins defined as outputs by Register 6 and 7. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, NOT the actual pin value.
Reading the port registers
In order to read data from the PCA9535, the bus master must first send the PCA9535 address with the least significant bit set to a logic 0 (see Figure 5 for device address). The command byte is sent after the address and determines which register will be accessed. After a restart, the device address is sent again but this time, the least significant bit is set to a logic 1. Data from the register defined by the command byte will then be sent by the PCA9535 (see Figures 8 , 9, and 10). Data is clocked into the register on the falling edge of the acknowledge clock pulse. After the first byte is read, additional bytes may be read but the data will now reflect the information in the other register in the pair. For example, if you read Input Port 1, then the next byte read would be Input Port 0. There is no limitation on the number of data bytes received in one read transmission but the final byte received, the bus master must not acknowledge the data.
Registers 4 and 5 — Polarity Inversion Registers
bit
default
N0.7
0
N0.6
0
N0.5
0
N0.4
0
N0.3
0
N0.2
0
N0.1
0
N0.0
0
bit
default
N1.7
0
N1.6
0
N1.5
0
N1.4
0
N1.3
0
N1.2
0
N1.1
0
N1.0
0
This register allows the user to invert the polarity of the Input Port register data. If a bit in this register is set (written with ‘1’), the Input Port data polarity is inverted. If a bit
