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PCA9534 8-bit I2C and SMBus, low power I/O port with interrupt
Product data sheet Supersedes data of 2003 Dec 02 2004 Sep 30
Philips Semiconductors
Philips Semiconductors
Product data sheet
8-bit I2C and SMBus low power I/O port with interrupt
PCA9534
DESCRIPTION
The PCA9534 is a16-pin CMOS device that provide 8 bits of General Purpose parallel Input/Output (GPIO) expansion for I2C/SMBus applications and was developed to enhance the Philips family of I2C I/O expanders. The improvements include higher drive capability, 5V I/O tolerance, lower supply current, individual I/O configuration, 400 kHz clock frequency, and smaller packaging. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, pushbuttons, LEDs, fans, etc.
FEATURES
• 8-bit I2C GPIO • Operating power supply voltage range of 2.3 V to 5.5 V • 5 V tolerant I/Os • Polarity inversion register • Active low interrupt output • Low stand-by current • Noise filter on SCL/SDA inputs • No glitch on power-up • Internal power-on reset • 8 I/O pins which default to 8 inputs • 0 kHz to 400 kHz clock frequency • ESD protection exceeds 2000 V HBM per JESD22-A114, • Latch-up testing is done to JESDEC Standard JESD78 which • Offered in three different packages: SO16, TSSOP16, and
HVQFN16 exceeds 100 mA 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
The PCA9534 consist of an 8-bit Configuration register (Input or Output selection); 8-bit Input register, 8-bit Output register and an 8-bit Polarity inversion register (Active HIGH or Active LOW operation). The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each Input or Output is kept in the corresponding Input or Output register. The polarity of the input port register can be inverted with the Polarity Inversion Register. All registers can be read by the system master. Although pin-to-pin and I2C address compatible with the PCF8574 series, software changes are required due to the enhancements and are discussed in Application Note AN469. The PCA9534 is identical to the PCA9554 except for the removal of the internal I/O pull-up resistor which greatly reduces power consumption when the I/Os are held LOW. The PCA9534 open-drain interrupt output is activated when any input state differs from its corresponding input port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine. Three hardware pins (A0, A1, A2) vary the fixed I2C address and allow up to eight devices to share the same I2C/SMBus.
ORDERING INFORMATION
PACKAGES 16-Pin Plastic SO (wide) 16-Pin Plastic TSSOP 16-Pin Plastic HVQFN TEMPERATURE RANGE –40 °C to +85 °C –40 °C to +85 °C –40 °C to +85 °C ORDER CODE PCA9534D PCA9534PW PCA9534BS TOPSIDE MARK PCA9534D PCA9534 9534 DRAWING NUMBER SOT162-1 SOT403-1 SOT629-1
Standard packing quantities and other packing data are available at www.standardproducts.philips.com/packaging. I2C is a trademark of Philips Semiconductors Corporation. SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I2C patent.
2004 Sep 30
2
Philips Semiconductors
Product data sheet
8-bit I2C and SMBus low power I/O port with interrupt
PCA9534
PIN CONFIGURATION — SO, TSSOP
A0 1 A1 2 16 VDD 15 SDA 14 SCL 13 INT 12 I/O7 11 I/O6 10 I/O5 9 I/O4
PIN CONFIGURATION — HVQFN
A1 16 A0 15 VDD 14 SDA 13 12 SCL 11 INT 10 I/O7 9 5 6 7 8 I/O6 I/O5
A2 I/O0 I/O1 I/O2
1 2 3 4
A2 3 I/O0 4 I/O1 5 I/O2 6 I/O3 7 VSS 8
I/O3
VSS I/O4
su01410
TOP VIEW
Figure 1. Pin configuration — SO, TSSOP
su01670
Figure 2. Pin Configuration — HVQFN
PIN DESCRIPTION
PIN NUMBER SO, TSSOP 1 2 3 4–7 8 9–12 13 14 15 16 HVQFN 15 16 1 2–5 6 7–10 11 12 13 14 SYMBOL A0 A1 A2 I/O0 to I/O3 VSS I/O4 to I/O7 INT SCL SDA VDD Address input 0 Address input 1 Address input 2 I/O0 to I/O3 Supply ground I/O4 to I/O7 Interrupt output (open drain) Serial clock line Serial data line Supply voltage FUNCTION
BLOCK DIAGRAM
PCA9534
A0 A1 A2 SCL SDA INPUT FILTER I2C/SMBUS CONTROL 8-BIT INPUT/ OUTPUT PORTS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 VDD POWER-ON RESET VSS LP FILTER NOTE: ALL I/Os ARE SET TO INPUTS AT RESET VCC
WRITE pulse READ pulse
INT
SU01783
Figure 3. Block diagram
2004 Sep 30
3
Philips Semiconductors
Product data sheet
8-bit I2C and SMBus low power I/O port with interrupt
PCA9534
REGISTERS Command Byte
Command 0 1 2 3 Protocol Read byte Read/write byte Read/write byte Read/write byte Function Input port register Output port register Polarity inversion register Configuration register
Power-on Reset
When power is applied to VDD, an internal power-on reset holds the PCA9534 in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA9534 registers and state machine will initialize to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the device. For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the operating voltage.
The command byte is the first byte to follow the address byte during a write transmission. It is used as a pointer to determine which of the following registers will be written or read.
Interrupt Output
The open-drain interrupt output is activated when one of the port pins change state and the pin is configured as an input. The interrupt is deactivated when the input returns to its previous state or the input port register is read. Note that changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the input port register.
Register 0 – Input Port Register
bit
default
I7 X
I6 X
I5 X
I4 X
I3 X
I2 X
I1 X
I0 X
This register is a read only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by Register 3. Writes to this register have no effect. The default value ‘X’ is determined by the externally applied logic level.
Register 1 – Output Port Register
bit
default
O7 1
O6 1
O5 1
O4 1
O3 1
O2 1
O1 1
O0 1
This register reflects the outgoing logic levels of the pins defined as outputs by Register 3. Bit values in this register have no effect on pins defined as inputs. Reads from this register return the value that is in the flip-flop controlling the output selection, NOT the actual pin value.
Register 2 – Polarity Inversion Register
bit
default
N7 0
N6 0
N5 0
N4 0
N3 0
N2 0
N1 0
N0 0
This register allows the user to invert the polarity of the Input Port Register data. If a bit in this register is set (written with ‘1’), the corresponding Input Port data is inverted. If a bit in this register is cleared (written with a ‘0’), the Input Port data polarity is retained.
Register 3 – Configuration Register
bit
default
C7 1
C6 1
C5 1
C4 1
C3 1
C2 1
C1 1
C0 1
This register configures the directions of the I/O pins. If a bit in this register is set, the corresponding port pin is enabled as an input with high impedance output driver. If a bit in this register is cleared, the corresponding port pin is enabled as an output. At reset, the I/Os are configured as inputs.
2004 Sep 30
4
Philips Semiconductors
Product data sheet
8-bit I2C and SMBus low power I/O port with interrupt
PCA9534
SIMPLIFIED SCHEMATIC OF I/O0 TO I/O7
DATA FROM SHIFT REGISTER CONFIGURATION REGISTER DATA FROM SHIFT REGISTER D FF WRITE CONFIGURATION PULSE WRITE PULSE CK Q D FF CK Q Q2 I/O0 TO I/O7 Q Q Q1 ESD PROTECTION DIODE OUTPUT PORT REGISTER DATA VDD
OUTPUT PORT REGISTER INPUT PORT REGISTER D FF READ PULSE CK Q Q
ESD PROTECTION DIODE
VSS
INPUT PORT REGISTER DATA
TO INT
DATA FROM SHIFT REGISTER WRITE POLARITY PULSE
D FF CK
Q
POLARITY REGISTER DATA
Q
POLARITY INVERSION REGISTER
SU01784
NOTE: At Power-on Reset, all registers return to default values. Figure 4. Simplified schematic of I/O0 to I/O7
I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V. If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the state of the output port register. Care should be exercised if an external voltage is applied to an I/O configured as an output because of the low impedance paths that exist between the pin and either VDD or VSS.
2004 Sep 30
5
Philips Semiconductors
Product data sheet
8-bit I2C and SMBus low power I/O port with interrupt
PCA9534
Device address
SLAVE ADDRESS
0
1
0
0
A2
A1
A0 R/W
FIXED
HARDWARE SELECTABLE
su01685
Figure 5. PCA9534 address
Bus transactions
Data is transmitted to the PCA9534 registers using the write mode as shown in Figures 6 and 7. Data is read from the PCA9534 registers using the read mode as shown in Figures 8 and 9. These devices do not implement an auto-increment function so once a command byte has been sent, the register which was addressed will continue to be accessed by reads until a new command byte has been sent.
SCL
1
2
3
4
5
6
7
8
9 command byte
slave address
data to port
SDA
S
0
1
0
0
A2
A1
A0
0 R/W
A
0
0
0
0
0
0
0
1
A acknowledge from slave
DATA 1
A
P
start condition
acknowledge from slave
acknowledge from slave
WRITE TO PORT
DATA 1 VALID DATA OUT FROM PORT tpv
su01421
Figure 6. WRITE to output port register
SCL
1
2
3
4
5
6
7
8
9
slave address
command byte
data to register
SDA
S
0
1
0
0
A2
A1
A0
0 R/W
A
0
0
0
0
0
0
1
1/0
A acknowledge from slave
DATA
A
P
start condition
acknowledge from slave
acknowledge from slave
DATA TO REGISTER
su01422
Figure 7. WRITE to configuration or polarity inversion registers
2004 Sep 30
6
Philip
