Integrated Quad Half-Bridge and Triple High-Side

Freescale Semiconductor Technical Data Document Number: MM908E621 Rev 4.0, 6/2007 Integrated Quad Half-Bridge and Triple High-Side with Embedded MCU and LIN for High End Mirror The 908E621 is an integrated single-package solution that includes a high-performance HC08 microcontroller with a SMARTMOSTM analog control IC. The HC08 includes flash memory, a timer, enhanced serial communications interface (ESCI), an analog-to-digital converter (ADC), serial peripheral interface (SPI) (only internal), and an internal clock generator module. The analog control die provides four half-bridge and three high-side outputs with diagnostic functions, a Hall-Effect sensor input, analog inputs, voltage regulator, window watchdog, and local interconnect network (LIN) physical layer. The single-package solution, together with LIN, provides optimal application performance adjustments and space-saving PCB design. It is well suited for the control of automotive high-end mirrors. Features • • • • • • • • • • • • High-Performance M68HC908EY16 Core 16 K Bytes of On-Chip Flash Memory, 512 Bytes of RAM Internal Clock Generator Module (ICG) Two 16-Bit, 2-Channel Timers 10-Bit Analog-to-Digital Converter (ADC) LIN Physical Layer Interface Autonomous MCU Watchdog / MCU Supervision One Analog Input with Switchable Current Source Four Low RDS(ON) Half-Bridge Outputs Three Low RDS(ON) High-Side Outputs Wake-Up Input One 2/3-Pin Hall-Effect Sensor Input • 12 Microcontroller I/Os >22µF 100nF 908E621 QUAD HALF-BRIDGE AND TRIPLE HIGHSIDE SWITCH WITH EMBEDDED MCU AND LIN DWB SUFFIX 98ARL10519D 54-TERMINAL SOICW-EP ORDERING INFORMATION Device MM908E621ACDWB/R2 Temperature Range (TA) -40°C to 85°C Package 54 SOICW-EP www.DataSheet4U.com LIN VSUP[1:8] L0 Wake Up Input VDDA/VREFH EVDD VDD 4,7µF 100nF HB1 HB2 M M 4 x Half Bridge Outputs VSSA/VREFL EVSS VSS RST_A RST IRQ_A IRQ PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 PTA3/KBD3 PTA4/KBD4 PTB3/AD3 PTB4/AD4 PTB5/AD5 PTC2/MCLK PTC3/OSC2 PTC4/OSC1 HB3 M HB4 HS1 HS2 HS3 High Side Output 1 High Side Output 2 High Side Output 3 µC PortA µC PortB µC PortC Internally connected HVDD A0 A0CST H0 Switched 5V output Analog Input with current source Analog Input current source trim 2-/3-pin hall sensor input Pull to ground for user mode µC PortD Internally connected PTD0/TACH0 PTD1/TACH1 PTE1/RxD GND[1:4] EP µC PortE TESTMODE Figure 1. 908E621 Simplified Application Diagram Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2007. All rights reserved. 2 VSSA/VREFL EVSS IRQ GND[1:4] VSUP[1:8] TESTMODE RST_A IRQ_A PTD0/TACH0 PTE1/RXD RST LIN Single Breakpoint Break Module Voltage Regulator PTE1/RXD PTE0/TXD TXD LIN Physical Layer Wakeup Port Reset Control High Side Driver & Diagnostic Switched VDD Driver & Diagnostic RXD 5-Bit Keyboard Interrupt Module 2-channel Timer Interface Module A 2-channel Timer Interface Module B Enhanced Serial Communication Interface Module Autonomous Watchdog Computer Operating Properly Module Serial Peripheral Interface Module Configuration Register Module Periodic Wake-up Timebase Module Arbiter Module Prescaler Module PTC1/MOSI Security Module BEMF Module PTA5/SPSCK PTC0/MISO PTA6/SS MISO MOSI SPSCK SS PTD0/TACH0 PWM HB2 Half Bridge Driver & Diagnostic VSS VDD HVDD L0 HS1[a:b] High Side Driver & Diagnostic HS2 High Side Driver & Diagnostic HS3 Internal Bus 24 Integral System Integration Module Single External IRQ Module Half Bridge Driver & Diagnostic HB1 Power-ON Reset Module SPI & CONTROL 908E621 EVDD INTERNAL BLOCK DIAGRAM VDDA/VREFH M68HC08 CPU CPU ALU Registers PTA0/KBD0 Control and Status Register, 64 Bytes User Flash, 15,872 Bytes User RAM, 512 Bytes Monitor ROM, 310 Bytes Flash programming (Burn-in), ROM 1024 Bytes PTA1/KBD1 User Flash Vector Space, 36 Bytes PTA2/KBD2 OSC2 Internal Clock OSC1 Generator Module PTA3/KBD3 RST PTA4/KBD4 IRQ PTB3/AD3 PTB4/AD4 VREFH VDDA 10 Bit Analog-toVREFL Digital Converter Module VSSA VDD POWER VSS PTB5/AD5 INTERNAL BLOCK DIAGRAM HB3 PTC2/MCLK Half Bridge Driver & Diagnostic PTC3/OSC2 PORT C DDRC DDRA PORT A PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTC1/MOSI PTC0/MISO PTD1/TACH1 PTD0/TACH0 PTE1/RXD PTE0/TXD Half Bridge Driver & Diagnostic HB4 PTC4/OSC1 PTD1/TACH1 FLSVPP DDRB PORT B HALLPORT PTB0/AD0 ADOUT Analog Multiplexer H0 A0 A0CST Analog Port with Current Source PORT D PORT E DDRD DDRE PTA6/SS PTA5/SPSCK PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB0/AD0 PTB0/AD0 Analog Integrated Circuit Device Data Freescale Semiconductor Figure 2. 908E621 Simplified Internal Block Diagram TERMINAL CONNECTIONS TERMINAL CONNECTIONS Transparent Top View of Package PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTB5/AD5 PTB4/AD4 PTB3/AD3 IRQ RST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 (PTD0/TACH0/BEMF -> PWM) PTD1/TACH1 RST_A IRQ_A LIN A0CST A0 GND1 HB4 VSUP1 GND2 HB3 VSUP2 NC NC TESTMODE GND3 HB2 VSUP3 Exposed Pad 41 40 39 38 37 36 35 34 33 32 31 30 29 28 PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 FLSVPP PTA3/KBD3 PTA4/KBD4 VDDA/VREFH EVDD EVSS VSSA/VREFL (PTE1/RXD <- RXD) VSS VDD HVDD L0 H0 HS3 VSUP8 HS2 VSUP7 HS1b HS1a VSUP6 VSUP5 GND4 HB1 VSUP4 Figure 3. Terminal Connections Table 1. Terminal Definitions A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 21. Die MCU Terminal 1 2 3 4 5 6 7 8 9 Terminal Name PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTB5/AD5 PTB4/AD4 PTB3/AD3 IRQ RST Formal Name Port C I/Os Definition These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. This terminal is an asynchronous external interrupt input terminal. This terminal is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. This terminal is the PWM signal test terminal. It internally connects the MCU PTD0/TACH0 terminal with the Analog die PWM input. Note: Do not connect in the application. MCU Port B I/Os MCU MCU MCU / Analog External Interrupt Input External Reset PWM signal (PTD0/TACH0/BEMF -> PWM) MCU MCU / Analog 10 44 PTD1/TACH1 (PTE1/RXD <- RXD) Port D I/Os LIN Transceiver Output This terminal is a special-function, bidirectional I/O port terminal that is shared with other functional modules in the MCU. This terminal is the LIN Transceiver output test terminal. It internally connects the MCU PTE1/RXD terminal with the Analog die LIN transceiver output terminal RXD. Note: Do not connect in the application. 908E621 Analog Integrated Circuit Device Data Freescale Semiconductor 3 TERMINAL CONNECTIONS Table 1. Terminal Definitions (continued) A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 21. Die MCU Terminal 45 48 MCU MCU 46 47 49 50 52 53 54 51 11 12 13 14 Terminal Name VSSA/VREFL VDDA/VREFH EVSS EVDD PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 FLSVPP RST_A IRQ_A Formal Name ADC Supply and Reference Terminals MCU Power Supply Terminals Port A I/Os Definition These terminals are the power supply and voltage reference terminals for the analog-to-digital converter (ADC). These terminals are the ground and power supply terminals, respectively. The MCU operates from a single power supply. These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. MCU Analog Analog Analog Analog Test Terminal Internal Reset Internal Interrupt Output LIN Bus Analog Input Trim Terminal For test purposes only. Do not connect in the application. This terminal is the bidirectional reset terminal of the analog die. This terminal is the interrupt output terminal of the analog die indicating errors or wake-up events. This terminal represents the single-wire bus transmitter and receiver. This is the Analog Input Trim Terminal for the A0 input. This is to connect a known fixed resistor value to trim the current source measurement. LIN A0CST Analog Analog 15 16 19 25 30 29 26 20 17 18 21 27 28 31 32 35 22 23 24 34 35 36 38 A0 GND1 GND2 GND3 GND4 HB1 HB2 HB3 HB4 VSUP1 VSUP2 VSUP3 VSUP4 VSUP5 VSUP6 VSUP7 NC NC TESTMODE HS1a HS1b HS2 HS3 H0 Analog Input Terminal This terminal is an analog input port with selectable source values. Power Ground Terminals These terminals are device power ground connections. Analog Half-Bridge Outputs This device includes power MOSFETs configured as four half-bridge driver outputs. These outputs may be configured for DC motor drivers, or as high-side and low-side switches. Note: The HB3 and HB4 have a lower RDS(ON) then HB1 and HB2. Analog Power Supply Terminals These terminals are device power supply terminals. – Analog Analog Analog No Connect TESTMODE Input High-Side HS1 Output High-Side HS2 Output High-Side HS3 Output Hall-Effect Sensor / General Purpose Input Wake-up Input Switchable VDD Output These terminals are not connected. Terminal for test purpose only. In application this terminal needs to be tied GND. This output terminal is a low RDS(ON) high-side switch. These output terminals are low RDS(ON) high-side switches. Analog 39 This terminal provides an input for a Hall-effect sensor or general purpose input. This terminal provides an high voltage input, which is wake-up capable. This terminal is a switchable VDD output for driving resistive loads requiring a regulated 5.0 V supply; e.g. potentiometers. Analog Analog 40 41 L0 HVDD 908E621 4 Analog Integrated Circuit Device Data Freescale Semiconductor TERMINAL CONNECTIONS