6-Lane 5-Port PCI Express Switch

www.DataSheet4U.com 6-Lane 5-Port PCI Express® Switch ® 89HPES6T5 Data Sheet Advance Information* Device Overview ◆ The 89HPES6T5 is a member of IDT’s PRECISE™ family of PCI Express switching solutions. The PES6T5 is an 6-lane, 5-port peripheral chip that performs PCI Express Base switching. It provides connectivity and switching functions between a PCI Express upstream port and up to four downstream ports and supports switching between downstream ports. ◆ ◆ Features ◆ ◆ High Performance PCI Express Switch – Six 2.5Gbps PCI Express lanes – Five switch ports – Upstream port is x2 – Downstream ports are x1 – Low-latency cut-through switch architecture – Support for Max Payload Sizes up to 256 bytes – One virtual channel – Eight traffic classes – PCI Express Base Specification Revision 1.1 compliant Flexible Architecture with Numerous Configuration Options – Automatic lane reversal on all ports – Automatic polarity inversion – Ability to load device configuration from serial EEPROM Legacy Support – PCI compatible INTx emulation – Bus locking ◆ ◆ Highly Integrated Solution – Requires no external components – Incorporates on-chip internal memory for packet buffering and queueing – Integrates six 2.5 Gbps embedded SerDes with 8B/10B encoder/decoder (no separate transceivers needed) Reliability, Availability, and Serviceability (RAS) Features – Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) – Supports ECRC and Advanced Error Reporting – Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O – Compatible with Hot-Plug I/O expanders used on PC motherboards Power Management – Utilizes advanced low-power design techniques to achieve low typical power consumption – Support PCI Power Management Interface specification (PCIPM 1.2) – Unused SerDes are disabled. – Supports Advanced Configuration and Power Interface Specification, Revision 2.0 (ACPI) supporting active link state Testability and Debug Features – Built in Pseudo-Random Bit Stream (PRBS) generator – Numerous SerDes test modes – Ability to read and write any internal register via the SMBus – Ability to bypass link training and force any link into any mode – Provides statistics and performance counters Block Diagram 5-Port Switch Core / 6 PCI Express Lanes Frame Buffer Route Table Port Arbitration Scheduler Transaction Layer Data Link Layer Transaction Layer Data Link Layer Transaction Layer Data Link Layer Transaction Layer Data Link Layer Transaction Layer Data Link Layer Mux / Demux Phy Logical Layer Phy Logical Layer Mux / Demux Phy Logical Layer Mux / Demux Phy Logical Layer Mux / Demux Phy Logical Layer Mux / Demux Phy Logical Layer SerDes SerDes SerDes SerDes SerDes SerDes (Port 0) (Port 2) (Port 3) Figure 1 Internal Block Diagram (Port 4) (Port 5) IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 28 © 2007 Integrated Device Technology, Inc. *Notice: The information in this document is subject to change without notice September 7, 2007 Advance Information IDT 89HPES6T5 Data Sheet ◆ ◆ 11 General Purpose Input/Output Pins – Each pin may be individually configured as an input or output – Each pin may be individually configured as an interrupt input – Some pins have selectable alternate functions Packaged in a 15mm x 15mm BGA with 1mm ball spacing Product Description Utilizing standard PCI Express interconnect, the PES6T5 provides the most efficient I/O connectivity solution for applications requiring high throughput, low latency, and simple board layout with a minimum number of board layers. It provides 3 GBps (24 Gbps) of aggregated, full-duplex switching capacity through 6 integrated serial lanes, using proven and robust IDT technology. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specification revision 1.1. The PES6T5 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification Revision 1.1. The PES6T5 can operate either as a store and forward or cut-through switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated resource management to allow efficient switching for applications requiring additional narrow port connectivity. North Bridge Memory Memory Memory Memory South Bridge x2 PES6T5 x1 GE LOM x1 GE LOM x1 GE x1 1394 Figure 2 I/O Expansion Application SMBus Interface The PES6T5 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES6T5, allowing every configuration register in the device to be read or written by an external agent. The master interface allows the default configuration register values of the PES6T5 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an external Hot-Plug I/O expander. Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In the slave interface, these address pins allow the SMBus address to which the device responds to be configured. In the master interface, these address pins allow the SMBus address of the serial configuration EEPROM from which data is loaded to be configured. The SMBus address is set up on negation of PERSTN by sampling the corresponding address pins. When the pins are sampled, the resulting address is assigned as shown in Table 1. 2 of 28 September 7, 2007 Advance Information Processor Processor IDT 89HPES6T5 Data Sheet Bit 1 2 3 4 5 6 7 Slave SMBus Address SSMBADDR[1] SSMBADDR[2] SSMBADDR[3] 0 SSMBADDR[5] 1 1 Master SMBus Address MSMBADDR[1] MSMBADDR[2] MSMBADDR[3] MSMBADDR[4] 1 0 1 Table 1 Master and Slave SMBus Address Assignment In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is never required. The PES6T5 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of the serial EEPROM. PES6T5 Processor SMBus Master Serial EEPROM ... Other SMBus Devices PES6T5 Processor SMBus Master ... Other SMBus Devices SSMBCLK SSMBDAT MSMBCLK MSMBDAT SSMBCLK SSMBDAT MSMBCLK MSMBDAT Serial EEPROM (a) Unified Configuration and Management Bus (b) Split Configuration and Management Buses Figure 3 SMBus Interface Configuration Examples Hot-Plug Interface The PES6T5 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES6T5 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES6T5 generates an SMBus transaction to the I/O expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin (alternate function of GPIO) of the PES6T5. In response to an I/O expander interrupt, the PES6T5 generates an SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander. 3 of 28 September 7, 2007 Advance Information As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure 3(a), the master and slave SMBuses are tied together and the PES6T5 acts both as a SMBus master as well as a SMBus slave on this bus. This requires that the SMBus master or processor that has access to PES6T5 registers supports SMBus arbitration. In some systems, this SMBus master interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBus arbitration. To support these systems, the PES6T5 may be configured to operate in a split configuration as shown in Figure 3(b). IDT 89HPES6T5 Data Sheet General Purpose Input/Output The PES6T5 provides 11 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM. Pin Description The following tables lists the functions of the pins provided on the PES6T5. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Signal PE0RP[1:0] PE0RN[1:0] PE0TP[1:0] PE0TN[1:0] PE2RP[0] PE2RN[0] PE2TP[0] PE2TN[0] PE3RP[0] PE3RN[0] PE3TP[0] PE3TN[0] PE4RP[0] PE4RN[0] PE4TP[0] PE4TN[0] PE5RP[0] PE5RN[0] PE5TP[0] PE5TN[0] PEREFCLKP PEREFCLKN Type I O I O I O I O I O I Name/Description PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pairs for port 0. PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pairs for port 0. PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit pair for port 2. PCI Express Port 3 Serial Data Receive. Differential PCI Express receive pair for port 3. PCI Express Port 3 Serial Data Transmit. Differential PCI Express transmit pair for port 3. PCI Express Port 4 Serial Data Receive. Differential PCI Express receive pair fo