3-Lane 3-Port PCI Express Switch

www.DataSheet4U.com 3-Lane 3-Port PCI Express® Switch ® 89HPES3T3 Data Sheet Advance Information* Device Overview ◆ The 89HPES3T3 is a member of IDT’s PRECISE™ family of PCI Express switching solutions. The PES3T3 is a 3-lane, 3-port peripheral chip that performs PCI Express Base switching. It provides connectivity and switching functions between a PCI Express upstream port and up to four downstream ports and supports switching between downstream ports. ◆ ◆ Features ◆ ◆ High Performance PCI Express Switch – Three 2.5Gbps PCI Express lanes – Three switch ports – x1 Upstream port – Two x1 Downstream ports – Low latency cut-through switch architecture – Support for Max payload sizes up to 256 bytes – One virtual channel – Eight traffic classes – PCI Express Base Specification Revision 1.1 compliant Flexible Architecture with Numerous Configuration Options – Automatic lane reversal on all ports – Automatic polarity inversion on all lanes – Ability to load device configuration from serial EEPROM Legacy Support – PCI compatible INTx emulation – Bus locking ◆ ◆ Highly Integrated Solution – Requires no external components – Incorporates on-chip internal memory for packet buffering and queueing – Integrates three 2.5 Gbps embedded SerDes with 8B/10B encoder/decoder (no separate transceivers needed) Reliability, Availability, and Serviceability (RAS) Features – Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) – Supports ECRC and Advanced Error Reporting – Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O – Compatible with Hot-Plug I/O expanders used on PC motherboards Power Management – Utilizes advanced low-power design techniques to achieve low typical power consumption – Supports PCI Power Management Interface specification (PCIPM 1.2) – Unused SerDes are disabled. – Supports Advanced Configuration and Power Interface Specification, Revision 2.0 (ACPI) supporting active link state Testability and Debug Features – Built in Pseudo-Random Bit Stream (PRBS) generator – Numerous SerDes test modes – Ability to bypass link training and force any link into any mode – Provides statistics and performance counters Block Diagram 3-Port Switch Core / 3 PCI Express Lanes Frame Buffer Route Table Port Arbitration Scheduler Transaction Layer Data Link Layer Transaction Layer Data Link Layer Transaction Layer Data Link Layer Mux / Demux Phy Logical Layer Mux / Demux Phy Logical Layer Mux / Demux Phy Logical Layer SerDes SerDes SerDes (Port 0) (Port 2) Figure 1 Internal Block Diagram (Port 3) IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 23 © 2007 Integrated Device Technology, Inc. *Notice: The information in this document is subject to change without notice September 7, 2007 Advance Information IDT 89HPES3T3 Data Sheet ◆ ◆ Five General Purpose Input/Output Pins – Each pin may be individually configured as an input or output – Each pin may be individually configured as an interrupt input – Four pins have selectable alternate functions Packaged in a 13mm x 13mm 144-ball BGA with 1mm ball spacing Product Description Utilizing standard PCI Express interconnect, the PES3T3 provides the most efficient fan-out solution for applications requiring x1 connectivity, low latency, and simple board layout with a minimum number of board layers. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specification 1.1. The PES3T3 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification Revision 1.1. The PES3T3 can operate either as a store and forward or cut-through switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated resource management to allow efficient switching for applications requiring additional narrow port connectivity and also some high-end connectivity. Processor Processor North Bridge Memory Memory Memory Memory South Bridge x1 PES3T3 x1 GE LOM x1 1394 Figure 2 I/O Expansion Application SMBus Interface The PES3T3 contains an SMBus master interface. This master interface allows the default configuration register values of the PES3T3 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an external Hot-Plug I/O expander. Two pins make up the SMBus master interface. These pins consist of an SMBus clock pin and an SMBus data pin. Hot-Plug Interface The PES3T3 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES3T3 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES3T3 generates an SMBus transaction to the I/O expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin (alternate function of GPIO) of the PES3T3. In response to an I/O expander interrupt, the PES3T3 generates an SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander. 2 of 23 September 7, 2007 Advance Information IDT 89HPES3T3 Data Sheet General Purpose Input/Output The PES3T3 provides 5 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin may be configured independently as an input or output through software control, and each GPIO pin is shared with another on-chip function. These alternate functions may be enabled via software or serial configuration EEPROM. Pin Description The following tables lists the functions of the pins provided on the PES3T3. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Signal PE0RP[0] PE0RN[0] PE0TP[0] PE0TN[0] PE2RP[0] PE2RN[0] PE2TP[0] PE2TN[0] PE3RP[0] PE3RN[0] PE3TP[0] PE3TN[0] PEREFCLKP PEREFCLKN Type I O I O I O I Name/Description PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pair for port 0. PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pair for port 0. PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit pair for port 2. PCI Express Port 3 Serial Data Receive. Differential PCI Express receive pair for port 3. PCI Express Port 3 Serial Data Transmit. Differential PCI Express transmit pair for port 3. PCI Express Reference Clock. Differential reference clock pair input. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic and on-chip SerDes. The frequency of the differential reference clock is 100 MHz. Table 1 PCI Express Interface Pins Signal MSMBCLK MSMBDAT Type I/O I/O Name/Description Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus. Master SMBus Data. This bidirectional signal is used for data on the master SMBus. Table 2 SMBus Interface Pins 3 of 23 September 7, 2007 Advance Information PCI Express Port 2 Serial Data Receive. Differential PCI Express receive pair for port 2. IDT 89HPES3T3 Data Sheet Signal GPIO[0] Type I/O Name/Description General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2 General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN0 Alternate function pin type: Input Alternate function: I/O Expander interrupt 0 input General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: GPEN Alternate function pin type: Output Alternate function: General Purpose Event (GPE) output General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P3RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 3 Table 3 General Purpose I/O Pins GPIO[1] GPIO[2] I/O I/O GPIO[7] I/O GPIO[9] I/O Signal APWRDISN CCLKDS Type I I Name/Description Auxiliary Power Disable Input. When this pin is active, it disables the device from using auxiliary power supply. Common Clock Downstream. The assertion of this pin indicates that all downstream ports are using the same clock source as that provided to downstream devices.This bit is used as the initial value of the Slot Clock Configuration bit in all of the Link Status Registers for downstream ports. The value may be override by modifying the SCLK bit in the downstream port’s PCIELSTS register. Common Clock Upstream. The assertion of this pin indicates that the upstream port is using the same clock source as the upstream device. This bit is used as the initial value of the Slot Clock Configuration bit in the Link Status Register for the upstream port. The value may be overridden by modifying the SCLK bit in the PA_PCIELSTS register. Fundamental Reset. Assertion of this signal resets all logic inside the PES3T3 and initiates a PCI Express fundamental reset. Table 4 System Pins (Part 1 of 2) CCLKUS I PERSTN I 4 of 23