12-lane 3-Port Non-Transparent PCI Express Switch

www.DataSheet4U.com 12-lane 3-Port Non-Transparent PCI Express® Switch ® 89HPES12NT3 Data Sheet Preliminary Information* Device Overview The 89HPES12NT3 is a member of the IDT PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O interconnect standard. The PES12NT3 is a 12-lane, 3-port peripheral chip that performs PCI Express Base switching with a feature set optimized for high performance applications such as servers, storage, and communications/networking. It provides high-performance I/O connectivity and switching functions between a PCIe® upstream port, a transparent downstream port, and a non-transparent downstream port. With non-transparent bridging (NTB) functionality, the PES12NT3 can be used standalone or as a chipset with IDT PCIe System Interconnect Switches in multi-host and intelligent I/O applications such as communications, storage, and blade servers where inter-domain communication is required. Features ◆ High Performance PCI Express Switch – Twelve PCI Express lanes (2.5Gbps), three switch ports – Delivers 48 Gbps (6 GBps) of aggregate switching capacity – Low latency cut-through switch architecture – Support for Max Payload size up to 2048 bytes – Supports one virtual channel and eight traffic classes – PCI Express Base specification Revision 1.0a compliant Flexible Architecture with Numerous Configuration Options – Port arbitration schemes utilizing round robin – Supports automatic per port link width negotiation (x4, x2, or x1) – Static lane reversal on all ports – Automatic polarity inversion on all lanes – Supports locked transactions, allowing use with legacy software – Ability to load device configuration from serial EEPROM – Ability to control device via SMBus ◆ Non-Transparent Port – Crosslink support on NTB port – Four mapping windows supported • Each may be configured as a 32-bit memory or I/O window • May be paired to form a 64-bit memory window – Interprocessor communication • Thirty-two inbound and outbound doorbells • Four inbound and outbound message registers • Two shared scratchpad registers – Allows up to sixteen masters to communicate through the nontransparent port – No limit on the number of supported outstanding transactions through the non-transparent bridge – Completely symmetric non-transparent bridge operation allows similar/same configuration software to be run – Supports direct connection to a transparent or non-transparent port of another switch ◆ Block Diagram 3-Port Switch Core Frame Buffer Route Table Port Arbitration Scheduler Transaction Layer Data Link Layer Transaction Layer Data Link Layer Transaction Layer Data Link Layer NonTransparent Bridge Multiplexer / Demultiplexer Phy Logical Layer Phy Logical Layer Phy Logical Layer Multiplexer / Demultiplexer Phy Logical Layer Phy Logical Layer Phy Logical Layer Multiplexer / Demultiplexer Phy Logical Layer Phy Logical Layer Phy Logical Layer ... ... ... SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes 12 PCI Express Lanes x4 Upstream Port and Two x4 Downstream Ports Figure 1 Internal Block Diagram IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.Inc. 1 of 29 © 2007 Integrated Device Technology, Inc. *Notice: The information in this document is subject to change without notice April 11, 2007 DSC 6929 IDT 89HPES12NT3 Data Sheet Highly Integrated Solution – Requires no external components – Incorporates on-chip internal memory for packet buffering and queueing – Integrates twelve 2.5 Gbps embedded full duplex SerDes, 8B/10B encoder/decoder (no separate transceivers needed) ◆ Reliability, Availability, and Serviceability (RAS) Features – Upstream port can be dynamically swapped with non-transparent downstream port to support failover applications – Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) – Supports ECRC pass-through in transparent and non-transparent ports – Supports Hot-Swap ◆ Power Management – Supports PCI Power Management Interface specification, Revision 1.1 (PCI-PM) – Unused SerDes are disabled ◆ Testability and Debug Features – Built in SerDes Pseudo-Random Bit Stream (PRBS) generator – Ability to read and write any internal register via the SMBus – Ability to bypass link training and force any link into any mode – Provides statistics and performance counters ◆ Two SMBus Interfaces – Slave interface provides full access to all software-visible registers by an external SMBus master – Master interface provides connection for an optional serial EEPROM used for initialization – Master interface is also used by an external Hot-Plug I/O expander – Master and slave interfaces may be tied together so the switch can act as both master and slave ◆ Eight General Purpose Input/Output pins ◆ Packaged in 19x19mm 324-ball BGA with 1mm ball spacing ◆ management. This includes round robin port arbitration, guaranteeing bandwidth allocation and/or latency for critical traffic classes in applications such as high throughput 10 GbE I/Os, SATA controllers, and Fibre Channel HBAs. Switch Configuration The PES12NT3 is a three port switch that contains 12 PCI Express lanes. Each of the three ports is statically allocated 4 lanes with ports labeled as A, B and C. Port A is the upstream port, port B is the transparent downstream port, and port C is the non-transparent downstream port. During link training, link width is automatically negotiated. Each PES12NT3 port is capable of independently negotiating to a x4, x2 or x1 width. Thus, the PES12NT3 may be used in virtually any three port switch configuration (e.g., {x4, x4, x4}, {x4, x2, x2}, {x4, x2, x1}, etc.). The PES12NT3 supports static lane reversal. For example, lane reversal for upstream port A may be configured by asserting the PCI Express Port A Lane Reverse (PEALREV) input signal or through serial EEPROM or SMBus initialization. Lane reversal for ports B and C may be enabled via a configuration space register, serial EEPROM, or the SMBus. Product Description Utilizing standard PCI Express interconnect, the PES12NT3 provides the most efficient high-performance I/O connectivity solution for applications requiring high throughput, low latency, and simple board layout with a minimum number of board layers. With support for non-transparent bridging, the PES12NT3, as a standalone switch or as a chipset with IDT PCIe System Interconnect Switches, enables multi-host and intelligent I/O applications requiring inter-domain communication. The PES12NT3 provides 48 Gbps (6 GBps) of aggregated, full-duplex switching capacity through 12 integrated serial lanes, using proven and robust IDT technology. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specification 1.0a. The PES12NT3 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification Revision 1.0a. The PES12NT3 can operate either as a store and forward or cut-through switch depending on the packet size and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated resource 2 of 29 *Notice: The information in this document is subject to change without notice April 11, 2007 IDT 89HPES12NT3 Data Sheet CPU PES12NT3 CPU PES12NT3 CPU PES12NT3 PCIe System Interconnect Switch PCIe System Interconnect Switch Embedded CPU Embedded CPU SATA / SAS Embedded CPU GbE / 10GigE FC Figure 2 PCIe System Interconnect Architecture Block Diagram Controller 1 CPU Controller 2 CPU PES12N3 Cache Maint. & Possible Data Flow x4 PCIe x4 PCIe PES12N3 x4 PCIe FC Controller FC Controller Storage To Server FC 2Gb/s and 4Gb/s FC 2Gb/s and 4Gb/s To Server Figure 3 Dual Host Storage System 3 of 29 April 11, 2007 IDT 89HPES12NT3 Data Sheet Pin Description The following tables list the functions of the pins provided on the PES12NT3. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Signal PEALREV Type I Name/Description PCI Express Port A Lane Reverse. When this bit is asserted, the lanes of PCI Express Port A are reversed. This value may be overridden by modifying the value of the PALREV bit in the PA_SWCTL register. PCI Express Port A Serial Data Receive. Differential PCI Express receive pairs for port A. PCI Express Port A Serial Data Transmit. Differential PCI Express transmit pairs for port A PCI Express Port B Lane Reverse. When this bit is asserted, the lanes of PCI Express Port B are reversed. This value may be overridden by modifying the value of the PBLREV bit in the PA_SWCTL register. PCI Express Port B Serial Data Receive. Differential PCI Express receive pairs for port B. PCI Express Port B Serial Data Transmit. Differential PCI Express transmit pairs for port B PCI Express Port C Lane Reverse. When this bit is asserted, the lanes of PCI Express Port C are reversed. This value may be overridden by modifying the value of the PCLREV bit in the PA_SWCTL register. PCI Express Port C Serial Data Receive. Differential PCI Express receive pairs for port C. PCI Express Port C Serial Data Transmit. Differential PCI Express transmit pairs for port C PCI Express Reference Clock. Differential reference clock pair input. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic and on-chip