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Atmel
Atmel

8951 Datasheet

8-Bit Microcontroller


8951 Datasheet Preview


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Features
Compatible with MCS-51Products
4 Kbytes of In-System Reprogrammable Flash Memory
Endurance: 1,000 Write/Erase Cycles
Fully Static Operation: 0 Hz to 24 MHz
Three-Level Program Memory Lock
128 x 8-Bit Internal RAM
32 Programmable I/O Lines
Two 16-Bit Timer/Counters
Six Interrupt Sources
Programmable Serial Channel
•• Low Power Idle and Power Down Modes
Description
The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4
Kbytes of Flash Programmable and Erasable Read Only Memory (PEROM). The
device is manufactured using Atmel’s high density nonvolatile memory technology
and is compatible with the industry standard MCS-51instruction set and pinout.
The on-chip Flash allows the program memory to be reprogrammed in-system or by
a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU
with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer
which provides a highly flexible and cost effective solution to many embedded control
applications.
Pin Configurations
(continued)
PDIP/Cerdip
INDEX
CORNER
P1.5
P1.6
P1.7
RST
(RXD) P3.0
NC
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
PQFP/TQFP
4 44 34 24 14 03 93 83 73 63 53 4
1 33
2 32
3 31
4 30
5 29
6 28
7 27
8 26
9 25
10 24
11 23
1
21
31
41
51
61
71
1
8
9
2
0
2
12
2
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD) P3.0
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
(WR) P3.6
(RD) P3.7
X TA L 2
X TA L 1
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VCC
39 P0.0 (AD0)
38 P0.1 (AD1)
37 P0.2 (AD2)
36 P0.3 (AD3)
35 P0.4 (AD4)
34 P0.5 (AD5)
33 P0.6 (AD6)
32 P0.7 (AD7)
31 EA/VPP
30 ALE/PROG
29 PSEN
28 P2.7 (A15)
27 P2.6 (A14)
26 P2.5 (A13)
25 P2.4 (A12)
24 P2.3 (A11)
23 P2.2 (A10)
22 P2.1 (A9)
21 P2.0 (A8)
PLCC/LCC
INDEX
CORNER
P1.5
P1.6
P1.7
RST
(RXD) P3.0
NC
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
6 4 2 44 42 40
7 5 3 1 43 4139
8 38
9 37
10 36
11 35
12 34
13 33
14 32
15 31
16 30
11781 92 02 12 22 32 42 52 62 72289
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
8-Bit
Microcontroller
with 4 Kbytes
Flash
AT89C51
0265E
Page 1

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Block Diagram
VCC
GND
RAM ADDR.
REGISTER
P0.0 - P0.7
PORT 0 DRIVERS
P2.0 - P2.7
PORT 2 DRIVERS
RAM
PORT 0
LATCH
PORT 2
LATCH
FLASH
B
REGISTER
ACC
STACK
POINTER
PROGRAM
ADDRESS
REGISTER
PSEN
ALE/PROG
EA / VPP
RST
TMP2
TMP1
ALU
PSW
INTERRUPT, SERIAL PORT,
AND TIMER BLOCKS
TIMING
AND
CONTROL
INSTRUCTION
REGISTER
PORT 1
LATCH
PORT 3
LATCH
OSC
PORT 1 DRIVERS
PORT 3 DRIVERS
P1.0 - P1.7
P3.0 - P3.7
BUFFER
PC
INCREMENTER
PROGRAM
COUNTER
DPTR
2 AT89C51
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AT89C51
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Description (Continued)
The AT89C51 provides the following standard features: 4
Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit
timer/counters, a five vector two-level interrupt architec-
ture, a full duplex serial port, on-chip oscillator and clock
circuitry. In addition, the AT89C51 is designed with static
logic for operation down to zero frequency and supports
two software selectable power saving modes. The Idle
Mode stops the CPU while allowing the RAM, timer/count-
ers, serial port and interrupt system to continue function-
ing. The Power Down Mode saves the RAM contents but
freezes the oscillator disabling all other chip functions until
the next hardware reset.
Pin Description
VCC
Supply voltage.
GND
Ground.
Port 0
Port 0 is an 8-bit open drain bidirectional I/O port. As an
output port each pin can sink eight TTL inputs. When 1s
are written to port 0 pins, the pins can be used as high-im-
pedance inputs.
Port 0 may also be configured to be the multiplexed low-
order address/data bus during accesses to external pro-
gram and data memory. In this mode P0 has internal pul-
lups.
Port 0 also receives the code bytes during Flash program-
ming, and outputs the code bytes during program verifica-
tion. External pullups are required during program verifica-
tion.
Port 1
Port 1 is an 8-bit bidirectional I/O port with internal pullups.
The Port 1 output buffers can sink/source four TTL inputs.
When 1s are written to Port 1 pins they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 1 pins that are externally being pulled low will source
current (IIL) because of the internal pullups.
Port 1 also receives the low-order address bytes during
Flash programming and program verification.
Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pullups.
The Port 2 output buffers can sink/source four TTL inputs.
When 1s are written to Port 2 pins they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 2 pins that are externally being pulled low will source
current (IIL) because of the internal pullups.
Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX
@ DPTR). In this application it uses strong internal pullups
when emitting 1s. During accesses to external data mem-
ory that use 8-bit addresses (MOVX @ RI), Port 2 emits
the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some
control signals during Flash programming and verification.
Port 3
Port 3 is an 8-bit bidirectional I/O port with internal pullups.
The Port 3 output buffers can sink/source four TTL inputs.
When 1s are written to Port 3 pins they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 3 pins that are externally being pulled low will source
current (IIL) because of the pullups.
Port 3 also serves the functions of various special features
of the AT89C51 as listed below:
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Alternate Functions
RXD (serial input port)
TXD (serial output port)
INT0 (extenal interrupt 0)
INT1 (extenal interrupt 1)
T0 (timer 0 extenal input)
T1 (timer 1 external input)
WR (extenal data memory write strobe)
RD (external data memory read strobe)
Port 3 also receives some control signals for Flash pro-
gramming and programming verification.
RST
Reset input. A high on this pin for two machine cycles
while the oscillator is running resets the device.
ALE/PROG
Address Latch Enable output pulse for latching the low
byte of the address during accesses to external memory.
This pin is also the program pulse input (PROG) during
Flash programming.
In normal operation ALE is emitted at a constant rate of
1/6 the oscillator frequency, and may be used for external
timing or clocking purposes. Note, however, that one ALE
pulse is skipped during each access to external Data
Memory.
If desired, ALE operation can be disabled by setting bit 0
of SFR location 8EH. With the bit set, ALE is active only
during a MOVX or MOVC instruction. Otherwise, the pin is
weakly pulled high. Setting the ALE-disable bit has no ef-
fect if the microcrontroller is in external execution mode.
PSEN
Program Store Enable is the read strobe to external pro-
gram memory.
(continued)
3
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Pin Description (Continued)
When the AT89C51 is executing code from external pro-
gram memory, PSEN is activated twice each machine cy-
cle, except that two PSEN activations are skipped during
each access to external data memory.
EA/VPP
External Access Enable. EA must be strapped to GND in
order to enable the device to fetch code from external pro-
gram memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA will be
internally latched on reset.
EA should be strapped to VCC for internal program execu-
tions.
This pin also receives the 12-volt programming enable
voltage (VPP) during Flash programming, for parts that re-
quire 12-volt VPP.
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively,
of an inverting amplifier which can be configured for use
as an on-chip oscillator, as shown in Figure 1. Either a
quartz crystal or ceramic resonator may be used. To drive
the device from an external clock source, XTAL2 should
be left unconnected while XTAL1 is driven as shown in
Figure 2. There are no requirements on the duty cycle of
the external clock signal, since the input to the internal
clocking circuitry is through a divide-by-two flip-flop, but
minimum and maximum voltage high and low time specifi-
cations must be observed.
Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-
chip peripherals remain active. The mode is invoked by
software. The content of the on-chip RAM and all the spe-
cial functions registers remain unchanged during this
mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset.
It should be noted that when idle is terminated by a hard-
ware reset, the device normally resumes program execu-
tion, from where it left off, up to two machine cycles before
the internal reset algorithm takes control. On-chip hard-
Figure 1. Oscillator Connections
C2
XTAL2
C1
XTAL1
GND
Notes: C1, C2 = 30 pF ± 10 pF for Crystals
= 40 pF ± 10 pF for Ceramic Resonators
Figure 2. External Clock Drive Configuration
Status of External Pins During Idle and Power Down
Mode
Idle
Idle
Power Down
Power Down
Program Memory
Internal
External
Internal
External
ALE
1
1
0
0
PSEN
1
1
0
0
PORT0
Data
Float
Data
Float
PORT1
Data
Data
Data
Data
PORT2
Data
Address
Data
Data
PORT3
Data
Data
Data
Data
4 AT89C51
Page 4
Part Number 8951
Manufactur Atmel
Description 8-Bit Microcontroller
Total Page 15 Pages
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