87C196CA 87C196CB 20 MHz ADVANCED 16-BIT CHMOS MICROCONTROLLER WITH INTEGRATED CAN 2 0
Automotive
Y
High Performance CHMOS 16-Bit CPU (up to 20 MHz Operation) Register-Register Architecture Up to 56 Kbytes of On-Chip EPROM Up to 1 5 Kbyte of On-Chip Register RAM Up to 512 Bytes of Additional RAM (Code RAM) Up to 16 Mbyte Linear Address Space Supports CAN (Controller Area Network) Specification 2 0 15 Message Objects of 8 Bytes Data Length 10-Bit A D with Sample Hold 38 Prioritized Interrupts Up to Seven 8-Bit (60) I O Ports Full Duplex Serial Port (SIO) with Dedicated Baudrate Generator
Y
Full Duplex Synchronous Serial I O Port (SSIO) Interprocessor Communication Slave Port Selectable Bus Timing Modes for Flexible Interfacing Oscillator Fail Detection Circuitry High Speed Peripheral Transaction Server (PTS) Two Dedicated 16-Bit High-Speed Compare Registers High Speed Capture Compare (EPA) Two Flexible 16-Bit Timer Counters Flexible 8- 16-Bit External Bus (Programmable) Programmable Bus (HLD HLDA) 1 4 ms 16 x 16 Multiply 2 4 ms 32 16 Divide
Y Y Y
Y
Y
Y Y
Y
Y Y
Y
Y Y Y
Y
Y Y Y Y
Y Y Y
b 40 C to a 125 C Ambient
Device 87C196CB 87C196CB 87C196CA Pins Package 84-Pin PLCC 100-Pin QFP 68-Pin PLCC EPROM 56K 56K 32K Reg RAM 1 5K 1 5K 1 0K Code RAM 512b 512b 256b I O 56 60 38 EPA 10 10 6 SIO Y Y Y SSIO Y Y Y CAN Y Y Y A D 8 8 6 Address Space 1 Mbyte 16 Mbyte 64 Kbyte
The 87C196CA CB are new members of the MCS 96 microcontroller family These devices are based upon the MCS 96 Kx Jx microcontroller product families with enhancements ideal for automotive and industrial applications The CA CB are the first devices in the Kx family to support networking through the integration of the CAN 2 0 (Controller Area Network) peripheral on-chip The 87C196CB offers the highests memory density of the MCS 96 microcontroller family with 56K of on-chip EPROM 1 5K of on-chip register RAM and 512 bytes of additional RAM (Code RAM) In addition the 87C196CB provides up to 16 Mbyte of Linear Address Space The 87C196CA is a sub-set of the CB offering 32K of on-chip EPROM up to 1 0K of on-chip register RAM and 256 bytes of additional RAM (Code RAM)
Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT
INTEL CORPORATION 1996
April 1996
Order Number 272405-004
87C196CA 87C196CB
The MCS 96 microcontroller family members are all high-performance microcontrollers with a 16-bit CPU The 87C196CB is composed of the high-speed (20 MHz) macrocore with up to 16 Mbyte linear address space 56 Kbytes of program EPROM up to 1 5 Kbytes of register RAM and up to 512 bytes of code RAM (16-bit addressing modes) with the ability to execute from this RAM space It supports the high-speed serial communications protocol CAN 2 0 with 15 message objects of 8 bytes data length an 8-channel 10-bit 3 LSB analog to digital converter with programmable S H times and conversion times k 20 ms at 20 MHz It has an asynchronous synchronous serial I O port (SIO) with a dedicated 16-bit baud rate generator an additional synchronous serial I O port (SSIO) with full duplex master slave transceivers a flexible timer counter structure with prescaler cascading and quadrature capabilities There are ten modularized multiplexed highspeed I O for capture and compare (called Event Processor Array) with 200 ns resolution and double buffered inputs and a sophisticated prioritized interrupt structure with programmable Peripheral Transaction Server (PTS) implementing several channel modes including single burst block transfers from any memory location to any memory location a PWM and PWM toggle mode to be used in conjunction with the EPA and an A D scan mode NOTICE This is an advance information data sheet The A C and D C parameters contained within this data sheet may change after full automotive temperature characterization of the device has been performed Contact your local sales office before finalizing the timing and D C characteristics of a design to verify you have the latest information
272405 – 30
Figure 1 8XC196CB Block Diagram
2
87C196CA 87C196CB
All thermal impedance data is approximate for static air conditions at 1 0W of power dissipation Values will change depending on operation conditions and application See the Intel Packaging Handbook (order number 240800) for a description of Intel’s thermal impedance test methodology
PROCESS INFORMATION
These devices are manufactured on P629 5 a CHMOS III-E process Additional process and reliability information is available in Intel’s Components Quality and Reliability Handbook Order Number 210997
272405 – 2
Figure 2 The 87C196CA CB Familiy Nomenclature
Thermal Characteristics
Device and Package AN87C196CB (84-Lead PLCC Package) AN87C196CA (68-Lead PLCC Package) iJA 35 0 C W 36 5 C W iJC 11 0 C W 10 0 C W
NOTES 1 iJA e Thermal resistance between junction and the surrounding environment (ambient) measurements are taken 1 ft away from case in air flow environment iJC e Thermal resistance between junction and package face (case) 2 All values of iJA and iJC may fluctuate depending on the environment (with or without airflow and how much airflow) and device power dissipation at temperature of operation Typical variations are g 2 C W 3 Values listed are at a maximum power dissipation of 1 0W
3
87C196CA 87C196CB
272405 – 14
Figure 3 84-Pin PLCC AN87C196CB Diagram
4
87C196CA 87C196CB
272405 – 33
Figure 4 100-Pin QFP AS87C196CB Diagram
5
87C196CA 87C196CB
272405 – 3
Figure 5 68-Pin PLCC 87C196CA Diagram
6
87C196CA 87C196CB
Symbol VCC VSS VSS1 VREF Main Supply Voltage ( a 5V)
Name and Function
Digital circuit ground (0V) There are 7 VSS pins CB (4 on CA) all of which MUST be connected to a single ground plane Reference for the A D converter ( a 5V) VREF is also the supply voltage to the analog portion of the A D converter and the logic used to read Port 0 Must be connected for A D and Port 0 to function Reference ground for the A D converter Must be held at nominally the same potential as VSS Programming voltage for EPROM parts It should be a 12 5V for programming It is also the timing pin for the return from powerdown circuit Connect this pin with a 1 mF capacitor to VSS and a 1Mohm resistor to VCC If this function is not used VPP may be tied to VCC Input of the oscillator inverter and the internal clock generator Output of the Oscillator Inverter Reset input to the chip Input low for at least 16 state times will reset the chip The subsequent low to high transition resynchronizes CLKOUT and commences a 10-state time sequence in which the PSW is cleared bytes are read from 2018H 201Ah and 201CH (if enabled) loading the CCB’s and a jump to location 2080H is executed Input high for normal operation RESET has an internal pullup A positive transition causes a non-maskable interrupt vector through memory location 203EH If not used this pin should be tied to VSS May be used by Intel Evaluation boards Input for memory select (External Access) EA equal to a high causes memory accesses to locations 0FF2000H through 0FFFFFFH to be directed to on-chip EPROM ROM EA equal to a low causes accesses to these locations to be directed to off-chip memory EA e a 12 5V causes execution to begin in the Programming Mode EA is latched at reset Selects between PLL mode or PLL bypass mode This pin must be either tied high or low PLLEN pin e 0 bypass PLL mode PLLEN pin e 1 places a 4x PLL at the input of the crystal oscillator Allows for a low frequency crystal to drive the device (i e 5 MHz e 20 MHz operation) Dual function I O ports have a system function as Synchronous Serial I O Two pins are clocks and two pins are data providing for full duplex capability Also LSIO when not used as SSIO Dual function I O pin Primary function is that of a bidirectional I O pin however it may also be used as a TIMER1 Direction input The TIMER1 will increment when this pin is high and decrements when this pin is low Dual function I O pin Primary function is that of a bidirectional I O pin however may also be used as a TIMER1 Clock input The TIMER1 will increment or decrement on both positive and negative edges of this pin Dual function I O port pins Primary function is that of bidirectional I O System function is that of High Speed capture and compare
ANGND VPP
XTAL1 XTAL2 RESET
NMI
EA
PLLEN (196CB only)
P6 4–6 7 SSIO
P6 3 T1DIR (CB only) P6 2 T1CLK (CB only) P6 0–6 1 EPA8– 9
7
87C196CA 87C196CB
Symbol P5 7 BUSWIDTH (CB only)
Name and Function Input for bus width selection If CCR bit 1 is a one and CCR1 bit 2 is a one this pin dynamically controls the Buswidth of the bus cycle in progress If BUSWIDTH is low an 8-bit cycle occurs if BUSWIDTH is high a 16-bit cycle occurs If CCR bit 1 is ‘‘0’’ and CCR1 bit 2 is ‘‘1’’ all bus cycles are 8-bit if CCR bit 1 is ‘‘1’’ and CCR1 bit 2 is ‘‘0’’ all bus cycles are 16-bit CCR bit 1 e ‘‘0’’ and CCR1 bit 2 e ‘‘0’’ is illegal Also an LSIO pin when not used as BUSWIDTH Ready input to lengthen external memory cycles for interfacing with slow or dynamic memory or for bus sharing If the pin is high CPU operation continues in a normal manner If the pin is low prior to the falling edge of CLKOUT the memory controller goes into a wait state mode until the next opositive transition in CLKOUT occurs with READY high When external memory is not used READY has no effect The max number of wait states inserted into the bus cycle is controlled by the CCR CCR1 Also an LSIO if READ
