I/O Controller Hub 4

Intel® 82801DB I/O Controller Hub 4 (ICH4) Datasheet May 2002 Document Number: 290744-001 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® I/O Controller Hub 4 (ICH4) chipset component may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I 2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM. 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Copyright © 2002, Intel Corporation 2 Intel® 82801DB ICH4 Datasheet Intel® 82801DB ICH4 Features s PCI Bus Interface s Power Management Logic s s s s s s s — Supports PCI Revision 2.2 Specification at 33 MHz — 133 MB/sec maximum throughput — Supports up to six master devices on PCI — One PCI REQ/GNT pair can be given higher arbitration priority (intended for external 1394 host controller) — Support for 44-bit addressing on PCI using DAC protocol Integrated LAN Controller — WfM 2.0 and IEEE 802.3 compliant — LAN Connect Interface (LCI) — 10/100 Mbit/sec ethernet support Integrated IDE Controller — Supports “Native Mode” register and interrupts — Independent timing of up to 4 drives, with separate primary and secondary IDE cable connections — Ultra ATA/100/66/33, BMIDE and PIO modes — Tri-state modes to enable swap bay USB — Includes three UHCI host controllers that support six external ports — New: Includes one EHCI high-speed USB 2.0 Host Controller that supports all six ports — New: Supports a USB 2.0 high-speed debug port — Supports wake-up from sleeping states S1–S5 — Supports legacy keyboard/mouse software AC-Link for Audio and Telephony CODECs — Supports AC ’97 2.3 — New: Third AC_SDATA_IN line for three codec support — New: Independent bus master logic for seven channels (PCM In/Out, Mic 1 input, Mic 2 input, modem in/out, S/PDIF out) — Separate independent PCI functions for audio and modem — Support for up to six channels of PCM audio output (full AC3 decode) — Supports wake-up events Interrupt Controller — Support up to eight PCI interrupt pins — Supports PCI 2.2 message signaled interrupts — Two cascaded 82C59 with 15 interrupts — Integrated I/O APIC capability with 24 interrupts — Supports serial interrupt protocol — Supports processor system bus interrupt delivery New: 1.5 V operation with 3.3 V I/O — 5 V tolerant buffers on IDE, PCI, USB overcurrent and legacy signals Timers Based on 82C54 — System timer, refresh request, speaker tone output s s s s s s s s s s — ACPI 2.0 compliant — ACPI-defined power states (C1–C2, S3–S5 ) — Supports Desktop S1 state (like C2 state, only STPCLK# active) — ACPI power management timer — PCI PME# support — SMI# generation — All registers readable/restorable for proper resume from 0 V suspend states External Glue Integration — Integrated pull-up, pull-down and series termination resistors on IDE, processor interface — Integrated Pull-down and Series resistors on USB Enhanced Hub Interface Buffers Improve Routing flexibility (Not available with all Memory Controller Hubs) Firmware Hub (FWH) Interface Supports BIOS memory size up to 8 MB Low Pin Count (LPC) Interface — Supports two Master/DMA devices. Enhanced DMA Controller — Two cascaded 8237 DMA controllers — PCI DMA: Supports PC/PCI — Includes two PC/PCI REQ#/GNT# pairs — Supports LPC DMA — Supports DMA collection buffer to provide Type-F DMA performance for all DMA channels Real-Time Clock — 256-byte battery-backed CMOS RAM System TCO Reduction Circuits — Timers to generate SMI# and Reset upon detection of system hang — Timers to detect improper processor reset — Supports ability to disable external devices SMBus — New: Hardware packet error checking — New: Supports SMBus 2.0 Specification — Host interface allows processor to communicate via SMBus — Slave interface allows an external microcontroller to access system resources — Compatible with most 2-wire components that are also I2C compatible GPIO — TTL, open-drain, inversion Package 31x31 mm 421 BGA The Intel® 82801DB ICH4 may contain design defects or errors known as errata which may cause the products to deviate from published specifications. Current characterized errata are available on request. Intel® 82801DB ICH4 Datasheet 3 System Configuration Processor AGP Host Controller Memory USB (Supports 6 USB 2.0 ports) IDE-Primary IDE-Secondary AC’97 Codec(s) LAN Connect GPIO Intel® 82801DB ICH4 Power Management Clock Generators Clock Generators System Management (TCO) SMBus/I2C PCI Bus Slot Firmware Hub(s) Firmware Hubs (1-8) Othe ASIC Other ASICs r s (Optional) LPC Interface Super I/O Super I/O 4 Intel® 82801DB ICH4 Datasheet Slot Contents 1 Introduction ...........................................................................................................27 1.1 1.2 About This Datasheet ....................................................................................27 Overview ........................................................................................................30 Hub Interface to Host Controller ....................................................................39 Link to LAN Connect ......................................................................................39 EEPROM Interface ........................................................................................40 Firmware Hub Interface .................................................................................40 PCI Interface ..................................................................................................40 IDE Interface ..................................................................................................43 LPC Interface .................................................................................................44 Interrupt Interface...........................................................................................44 USB Interface.................................................................................................45 Power Management Interface........................................................................46 Processor Interface........................................................................................47 SMBus Interface ............................................................................................48 System Management Interface ......................................................................48 Real Time Clock Interface..............................................................................49 Other Clocks ..................................................................................................49 Miscellaneous Signals ...................................................................................49 AC-Link ..........................................................................................................50 General Purpose I/O ......................................................................................51 Power and Ground.........................................................................................52 Pin Straps ......................................................................................................53 2.20.1 Functional Straps ..............................................................................53 2.20.2 External RTC Circuitry ......................................................................54 2.20.3 V5REF / Vcc3_3 Sequencing Requirements ....................................54 2.20.4 Test Signals ......................................................................................55 Power Planes.................................................................................................57 Integrated Pull-Ups and Pull-Downs ..............................................................58 IDE Integrated Series Termination Resistors.................................................58 Output and I/O Signals Planes and S