82801AB (ICH0) I/O Controller Hub

Intel® 82801AA (ICH) and Intel® 82801AB (ICH0) I/O Controller Hub Datasheet June 1999 Order Number: 290655-002 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. The Intel® 82801AA (ICH) and Intel® 82801AB (ICH0) may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available upon request. I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by: calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 1999 *Third-party brands and names are the property of their respective owners. ii 82801AA and 82801AB Datasheet Intel® 82801AA (I CH) and Intel® 82801AB (ICH0) Features s PCI Bus Interface — Supports PCI at 33 MHz — Supports PCI Rev 2.2 Specification — 133 MByte/sec Maximum Throughput — Master PCI Device Support: up to 6 for the ICH and up to 4 for the ICH0 Integrated IDE Controller — Independent Timing of Up to 4 Drives — The ICH Supports Ultra ATA/66 Mode (66 Mbytes/sec) — Supports Ultra ATA/33 Mode (33 Mbytes/sec) — PIO Mode 4 Transfers up to 14 Mbytes/s — Separate IDE Connections for Primary and Secondary Cables — Implements Write Ping-Pong Buffer for faster write performance USB — UHCI Implementation With 2 Ports — Supports Wake-up From Sleeping States S1-S4 — Supports Legacy Keyboard/Mouse Software — USB Revision 1.1 Compliant AC'97 Link for Audio and Telephony CODECs — AC’97 2.1 Compliant — 5 Independent Bus Master Logic for PCM In, PCM Out, Mic Input, Modem In, Modem Out — Separate Independent PCI Functions for Audio and Modem — Supports wake-up events Interrupt Controller — Two Cascaded 82C59 — Integrated I/O APIC Capability — 15 Interrupts Support in 8259 Mode, 24 Supported in I/O APIC Mode. — Supports Serial Interrupt Protocol Timers Based on 82C54 System Timer, Refresh Request, Speaker Tone Output 3.3 V Operation With 5 V Tolerant Buffers for IDE and PCI signals. 241 BGA package s s GPIO — TTL, Open-Drain, Inversion Power Management Logic — ACPI 1.0 Compliant — Support for APM-Based Legacy Power Management for Non-ACPI Implementations — ACPI Defined Power States (S1, S3, S4, S5) — ACPI Power Management Timer — SMI# Generation — All Registers Readable/Restorable for Proper Resume from 0 V Suspend States — PCI PME# Low Pin count (LPC) Interface — Allows Connection of Legacy ISA and X-Bus Devices such as Super I/O — Supports Two Master/DMA Devices. Enhanced DMA Controller — Two Cascaded 8237 DMA Controllers — PCI DMA: Supports PC/PCI — Includes Two PC/PCI REQ#/GNT# Pairs — Supports LPC DMA — Supports DMA Collection Buffer to Provide Type-F DMA Performance for All DMA Channels Real - Time Clock — 256-byte Battery-Backed CMOS RAM — Hardware implementation to indicate Century Rollover System TCO Reduction Circuits — Timers to Generate SMI# and Reset Upon Detection of locked system — Timers to Detect Improper Processor Reset — Integrated Processor Frequency Strap Logic SM Bus — Host Interface Allows Processor to Communicate via SM Bus — Compatible With Most 2-Wire Components that are Also I2C compatible Supports ISA Bus via External PCI-ISA Bridge Firmware Hub (FWH) Interface The 82801AA provides Alert On LAN* Support s s s s s s s s s s s s s s s s This datasheet describes the Intel® 82801AA and Intel® 82801AB components. Non-shaded areas describe the functionality of both components. Shading,as is shown here, indicates differences between the two components. The Intel® 82801AA and Intel® 82801AB may contain design defects or errors known as errata which may cause the products to deviate from published specifications. Current characterized errata are available on request. 82801AA and 82801AB Datasheet iii Intel® 82801AA (ICH) and Intel® 82801AB (ICH0) Simplified Block Diagram AD[31:0] C/BE[3:0]# DEVSEL# FRAME# IRDY# TRDY# STOP# PAR (ICH) PERR#/GPIO7 REQ[0:3]# (ICH) REQ[4]# (ICH) REQ5#/REQB#/GPIO1 REQA# GNT[0:3]# (ICH) GNT[4]# (ICH) GNT5#/GNTB#/GPIO17 GNTA# PCICLK PCIRST# PLOCK# SERR# PME# A20M# CPUSLP# FERR# IGNNE# INIT# INTR NMI SMI# STPCLK# RCIN# A20GATE SERIRQ PIRQ[A:D]# IRQ[14:15] APICCLK APICD[1:0] USBP1P USBP1N USBP0P USBP0N OC[1:0]# RTCX1 RTCX2 VBIAS CLK14 CLK48 CLK66 SPKR RTCRST# PDCS1# SDCS1# PDCS3# SDCS3# PDA[2:0] SDA[2:0] PDD[15:0] SDD[15:0] PDDREQ SDDREQ PDDACK# SDDACK# PDIOR# SDIOR# PDIOW# SDIOW# PIORDY SIORDY THRM# SLP_S3/GPIO24 SLP_S5# PWROK PWRBTN# RI# RSMRST# SUS_STAT#/GPIO25 SUSCLK/GPIO26 (ICH) AC_RST# AC_SYNC AC_BIT_CLK AC_SDOUT AC_SDIN0 AC_SDIN1/GPIO9 HL[10:0] (ICH0); HL11:0] (ICH) HL_STB HL_STB# HLCOMP FWH[3:0]/LAD[3:0] FWH[4]/LFRAME# LAD[3:0]/FWH[4] LFRAME#/FWH[4] LDRQ[0]# LDRQ[1]#/GPIO[8] SMBDATA SMBCLK SMBALERT#/GPIO[11] IDE Interface PCI Interface Power Mgnt CPU Interface AC'97 Link Interrupt Hub Interface USB Firmware Hub LPC Interface RTC SMBus Interface Clocks Misc. Signals System Mgnt INTRUDER# ALERTCLK/GPIO[27] (ICH) ALERTDATA/GPIO[28] (ICH) GPIO[0,1,5:13] GPIO[16,17, 21:26] GPIO[27:28] General Purpose I/O Note 1. Shaded areas: PERR#, REQ[4,5]#, GNT[4,5]#, HL[11], SUSCLK, ALERTCLK, and ALERTDATA are ICH (82801AA) Signals only. The associated GPIOx signals are multiplexed on the ICH and are non-multiplexed on ICH0. 2. General Purpose I/O Unit. Some GPIO signals are multiplexed with signals in other functional units. iv 82801AA and 82801AB Datasheet System Block Diagram Processor Graphics Controller1 Host Controller Main Memory Hub Interface PCI Slots SMBus Device(s) SMBus PCI Bus AC'97 Codec(s) (optional) AC'97 2.1 I/O Controller Hub - 82801AB (ICH0) or - 82801AA (ICH) PCI Agent ISA Bridge (optional) ATA/66 for ICH ATA/33 for ICH0 4 IDE Drives 2xUSB GPIO LPC I/F Super I/O (required) Keyboard, Mouse, FD, PP, SP, IR FWH Note: 1. The 82801AB ICH0 is intended to be used with the Intel ® 82810 Graphics and Memory Controller (GMCH) as the Host Controller. The graphics controller is integrated on the GMCH. 82801AA and 82801AB Datasheet v Contents 1 Introduction ................................................................................................................1-1 1.1 1.2 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 2.17 2.18 About this Manual .........................................................................................1-1 Overview.......................................................................................................1-3 Hub Interface ................................................................................................2-1 Firmware Hub Interface ................................................................................2-1 PCI Interface.................................................................................................2-2 IDE Interface.................................................................................................2-4 Low Pin Count (LPC) Interface .....................................................................2-5 Interrupt Interface .........................................................................................2-6 USB Interface ...............................................................................................2-6 Power Management Interface.......................................................................2-7 Processor Interface.......................................................................................2-8 SMBus Interface ...........................................................................................2-9 System Management Interface.....................................................................2-9 Real Time Clock Interface ............................................................................2-9 Other Clocks ...............................................................................................2-10 Miscellaneous Signals ................................................................................2-10 AC’97 Link ..................................................................................................2-10 General Purpose I/O...................................................................................2-11 Power and Ground......................................................................................2-12 Pin Straps ...................................................................................................2-12 2.18.1 Functional Strap.............................................................................2-12 2.18.2 Test Straps ....................................................................................2-13 2.18.