Description
E T T INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC) T Accelerated Graphics Port (A.G.P.) Interface  A.G.P. Specification Compliant  A.G.P. 66/133 MHz 3.3V Devices Supported  Synchronous Coupling to the Host Bus Frequency PCI Bus Interface  PCI Revision 2.1 Interface Compliant  Greater Than 100-MBps Data Streaming for PCI-to-DRAM Accesses  Integrated Arbiter With MultiTransaction PCI Arbitration Acceleration Hooks  Five PCI Bus Masters are Supported in Addition to the Host and PCI-toISA I/O Bridge  Delayed Transaction Support  PCI Parity Checking and Generation Support Data Buffering For Increased Performance  Extensive CPU-to-DRAM, PCI-toDRAM, and A.G.P.-to-DRAM Write Data Buffering  CPU-to-A.G.P., PCI-to-A.G.P., and A.G.P.-to-PCI Data Buffering  Write Combining Support for CPU-to-PCI Burst Writes  Supports Concurrent Host, PCI, and A.G.P. Transactions to Main Memory System Management Mode (SMM) Compliant 492 Pin BGA Package Supports the Pentium® II Processor at a Bus Frequency of 66 MHz  Supports 32-Bit Addressing  Optimized In-Order and Request Queue  Full Symmetric Multi-Processor (SMP) Protocol for Up to Two Processors  Dynamic Deferred Transaction Support  GTL+ Compliant Host Bus Supports WC Cycles Integrated DRAM Controller  EDO (Extended Data Out), and Synchronous DRAM Support  Supports a Maximum Memory Size of 512 MB With SDRAM, or 1 GB With EDO  64/72-bit Path to Memory  Configurable DRAM Interface  Support for Auto Detection of Memory Type: (DIMM Serial Presence Detect)  8 RAS Lines Available  Support for 4-, 16- and 64-Mbit DRAM devices  Support for Symmetrical and Asymmetrical DRAM Addressing  Configurable Support for ECC/EC  ECC With Single Bit Error Correction and Multiple Bit Error Detection  Read-Around-Write Support for Host and PCI DRAM Read Accesses  Supports 3.3V DRAMs T T T T The 82443LX (PAC) is the first generation of desktop AGPset designed for the Pentium® II processor. The 82443LX PCI A.G.P. Controller (PAC) integrates a Host-to-PCI bridge, optimized DRAM controller and data path, and an Accelerated Graphics Port (A.G.P.) interface. A.G.P. is a high performance, component level interconnect, targeted at 3D graphics applications and based on a set of performance enhancements to PCI. The I/O subsystem portion of the PAC platform is based on the PIIX4, a highly integrated version of the Intel’s PCI-to-ISA bridge family. PAC is developed as the ultimate Pentium II processor platform and is targeted for emerging 3D graphics and multimedia applications. The 440LX AGPset may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. January 1998 Order Number: 290564-002 INTEL 82443LX (PAC) E Host Interface PCI Bus Interface (PCI #0) AD[31:0] C/BE[3:0]# FRAME# TRDY# IRDY# DEVSEL# PAR PERR# SERR# PLOCK# STOP# PHLD# PHLDA# WSC# REQ[4:0]# GNT[4:0]# GAD[31:0] GC/BE[3:0]# GFRAME# GIRDY# GTRDY# GSTOP# GDEVSEL# GPERR# GSERR# GREQ# GGNT# GPAR PIPE# SBA[7:0] RBF# STOP# ST[2:0] ADSTB_A ADSTB_B SBSTB A[31:3]# ADS# DPRI# DNR# CPURST# DBSY# DEFER# HD[63:0]# HIT# HITM# HLOCK# HREQ[4:0]# HTRDY# INIT# RS[2:0]# RCSA[5:0]# RCSA[7:6]#/MAB[3:2] RCSB[7:0]#/MAB[13:6] CDQA[7:0]# CDQB1# CDQB5# SRAS[2:0]# SRAS3#/MAB5 SCAS[2:0]# SCAS3#/MAB4 MAA[13:0] MAB[1:0] WE[3:0]# MD[63:0] MECC[7:0] CKE DRAM Interface A.G.P. Interface HCLKIN PCLKIN GTLREF AGPREF VTT REF5V RSTIN# CRESET# ECCERR# BREQ0# TESTIN# Clocks, Reset, Test, and Misc. LX_BLK 82443LX Block Diagram 2 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 440LX AGPset may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. *Third-party brands and names are the property of their respective owners. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation Call 1-800-548-4725 or visit the Intel web site at http:www.intel.com COPYRIGHT © INTEL CORPORATION, 1997-1998 CG-041493 INTEL 82443LX (PAC) CONTENTS E PAGE 1.0. OVERVIEW..............................................................................................................................................9 2.0. SIGNAL DESCRIPTION ........................................................................................................................ 13 2.1. PAC Signals ....................................................................................................................................... 14 2.1.1. HOST INTERFACE SIGNALS ..................................................................................................... 14 2.1.2. DRAM INTERFACE SIGNALS..................................................................................................... 15 2.1.3. PCI INTERFACE SIGNALS ......................................................................................................... 20 2.1.4. A.G.P. INTERFACE SIGNALS..................................................................................................... 22 2.1.5. CLOCKS, RESET, AND MISCELLANEOUS SIGNALS ............................................................... 25 2.2. Power-Up/Reset Strapping Options .................................................................................................... 26 2.3. State of PAC Output and Bi-directional Signals During Hard Reset .................................................... 27 3.0. REGISTER DESCRIPTION.................................................................................................................... 29 3.1. Register Access ................................................................................................................................. 30 3.1.1. CONFADD—CONFIGURATION ADDRESS REGISTER............................................................. 30 3.1.2. CONFDATA—CONFIGURATION DATA REGISTER .................................................................. 31 3.1.3. CONFIGURATION SPACE MECHANISM ................................................................................... 31 3.1.3.1. Routing the Configuration Accesses to PCI or A.G.P. ........................................................... 31 3.1.3.2. PCI Bus Configuration Mechanism........................................................................................ 31 3.1.3.3. Mapping of Configuration Cycles on A.G.P. .......................................................................... 32 3.2. PCI Configuration Space (Device 0 and Device 1).............................................................................. 32 3.3. Register Set—Device 0 (Host-to-PCI Bridge) ..................................................................................... 35 3.3.1. VID—VENDOR IDENTIFICATION REGISTER (DEVICE 0) ........................................................ 35 3.3.2. DID—DEVICE IDENTIFICATION REGISTER (DEVICE 0) .......................................................... 35 3.3.3. PCICMD—PCI COMMAND REGISTER (DEVICE 0) ................................................................... 36 3.3.4. PCISTS—PCI STATUS REGISTER (DEVICE 0)......................................................................... 37 3.3.5. RID—REVISION IDENTIFICATION REGISTER (DEVICE 0) ...................................................... 38 3.3.6. SUBC—SUB-CLASS CODE REGISTER (DEVICE 0) ................................................................. 38 3.3.7. BCC—BASE CLASS CODE REGISTER (DEVICE 0).................................................................. 38 3.3.8. MLT—MASTER LATENCY TIMER REGISTER (DEVICE 0) ....................................................... 39 3.3.9. HDR—HEADER TYPE REGISTER (DEVICE 0).......................................................................... 39 3.3.10. APBASE—APERTURE BASE CONFIGURATION REGISTER (DEVICE 0) .............................. 39 3.3.11. CAPPTR—CAPABILITIES POINTER (DEVICE 0)..................................................................... 40 3.3.12. PACCFG—PAC CONFIGURATION REGISTER (DEVICE 0) .................................................... 41 3.3.13. DBC—DATA BUFFER CONTROL REGISTER (DEVICE 0) ...................................................... 42 3.3.14. DRT—DRAM ROW TYPE REGISTER (DEVICE 0) ................................................................... 43 3.3.15. DRAMC—DRAM CONTROL REGISTER (DEVICE 0) ............................................................... 44 3.3.16. DRAMT—DRAM TIMING REGISTER (DEVICE 0) .................................................................... 44 3.3.17. PAM—PROGRAMMABLE ATTRIBUTE MAP REGISTERS (PAM[6:0]) (DEVICE 0) ................. 46 3.3.18. DRB—DRAM ROW BOUNDARY REGISTERS (DEVICE 0)...................................................... 48 4 E INTEL 82443LX (PAC) 3.3.19. FDHC—FIXED DRAM HOLE CONTROL REGISTER (DEVICE 0) ....

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