CHMOS SINGLE-CHIP FLOPPY DISK CONTROLLER

www.DataSheet4U.com 82077AA CHMOS SINGLE-CHIP FLOPPY DISK CONTROLLER Y Single-Chip Floppy Disk Solution 100% PC AT Compatible 100% PS 2 Compatible 100% PS 2 Model 30 Compatible Integrated Drive and Data Bus Buffers Integrated Analog Data Separator 250 Kbits sec 300 Kbits sec 500 Kbits sec 1 Mbits sec High Speed Processor Interface Perpendicular Recording Support Y Y Integrated Tape Drive Support 12 mA Host Interface Drivers 40 mA Disk Drivers Four Fully Decoded Drive Select and Motor Signals Programmable Write Precompensation Delays Addresses 256 Tracks Directly Supports Unlimited Tracks 16 Byte FIFO 68-Pin PLCC (See Packaging Spec Order 240800 Package Type N) Y Y Y Y Y Y Y Y The 82077AA floppy disk controller has completely integrated all of the logic required for floppy disk control The 82077AA a 24 MHz crystal a resistor package and a device chip select implements a PC AT or PS 2 solution All programmable options default to compatible values The dual PLL data separator has better performance than most board level discrete PLL implementations The FIFO allows better system performance in multi-master systems (e g PS 2 EISA) The 82077AA is available in three versions 82077AA-5 82077AA and 82077AA-1 82077AA-1 has all features listed in this data sheet It supports both tape drives and 4 Mb floppy drives The 82077AA supports 4 Mb floppy drives and is capable of operation at all data rates through 1 Mbps The 82077AA-5 supports 500 300 250 Kbps data rates for high and low density floppy drives The 82077AA is fabricated with Intel’s CHMOS III technology and is available in a 68-lead PLCC (plastic) package 290166 – 1 Figure 1 82077AA Pinout PS 2 and PC AT are trademarks of IBM May 1994 Order Number 290166-007 82077AA CHMOS Single-Chip Floppy Disk Controller CONTENTS 1 0 INTRODUCTION 1 1 Oscillator 1 2 Perpendicular Recording Mode 2 0 MICROPROCESSOR INTERFACE 2 1 Status Data and Control Registers 2 1 1a Status Register A (SRA PS 2 Mode) 2 1 1b Status Register A (SRA Model 30 Mode) 2 1 2a Status Register B (SRB PS 2 Mode) 2 1 2b Status Register B (SRB Model 30 Mode) 2 1 3 Digital Output Register (DOR) 2 1 4 Tape Drive Register (TDR) 2 1 5 Datarate Select Register (DRS) 2 1 6 Main Status Register (MSR) 2 1 7 FIFO (Data) 2 1 8a Digital Input Register (DIR PC-AT Mode) 2 1 8b Digital Input Register (DIR PS 2 Mode) 2 1 8c Digital Input Register (DIR Model 30 Mode) 2 1 9a Configuration Control Register (CCR PC AT and PS 2 Modes) 2 1 9b Configuration Control Register (CCR Model 30 Mode) 2 2 RESET 2 2 1 Reset Pin (‘‘Hardware’’) Reset 2 2 2 DOR Reset vs DSR Reset (‘‘Software’’ Reset) PAGE 7 8 8 8 8 8 8 9 9 9 9 10 10 11 11 11 12 CONTENTS 2 3 DMA Transfers 3 0 DRIVE INTERFACE 3 1 Cable Interface 3 2 Data Separator 3 2 1 Jitter Tolerance 3 2 2 Locktime (tLOCK) 3 2 3 Capture Range 3 2 4 Reference Filter 3 3 Write Precompensation 4 0 CONTROLLER PHASES 4 1 Command Phase 4 2 Execution Phase 4 2 1 Non-DMA Mode Transfers from the FIFO to the Host 4 2 2 Non-DMA Mode Transfers from the Host to the FIFO 4 2 3 DMA Mode Transfers from the FIFO to the Host 4 2 4 DMA Mode Transfers from the Host to the FIFO 4 2 5 Data Transfer Termination 4 3 Result Phase 5 0 COMMAND SET DESCRIPTIONS 5 1 Data Transfer Commands 5 1 1 Read Data 5 1 2 Read Deleted Data 5 1 3 Read Track 5 1 4 Write Data 5 1 5 Write Deleted Data 5 1 6 Verify 5 1 7 Format Track 5 1 7 1 Format Fields 5 1 8 Scan Commands PAGE 12 12 13 13 14 14 14 15 15 15 15 16 16 16 16 17 17 17 17 24 24 25 26 26 26 26 27 28 29 12 12 12 12 12 2 CONTENTS 5 0 COMMAND SET DESCRIPTIONS (Continued) 5 2 Control Commands 5 2 1 Read ID 5 2 2 Recalibrate 5 2 3 Seek 5 2 4 Sense Interrupt Status 5 2 5 Sense Drive Status 5 2 6 Specify 5 2 7 Configure 5 2 8 Version 5 2 9 Relative Seek 5 2 10 DUMPREG 5 2 11 Perpendicular Mode Command 5 3 Command Set Enhancements 5 3 1 Perpendicular Mode 5 3 2 Lock 5 3 3 Enhanced DUMPREG Command 6 0 STATUS REGISTER ENCODING 6 1 Status Register 0 6 2 Status Register 1 6 3 Status Register 2 6 4 Status Register 3 7 0 COMPATIBILITY 7 1 Register Set Compatibility 7 2 PS 2 vs AT vs Model 30 Mode 7 2 1 PS 2 Mode 7 2 2 PC AT Mode 7 2 3 Model 30 Mode 7 3 Compatibility with the FIFO 7 4 Drive Polling PAGE CONTENTS 8 0 PROGRAMMING GUIDELINES 8 1 Command and Result Phase Handshaking 8 2 Initialization 8 3 Recalibrates and Seeks 8 4 Read Write Operations 8 5 Formatting 8 6 Verifies PAGE 39 39 40 42 43 43 46 46 46 46 48 50 50 51 51 52 52 52 53 30 30 30 30 31 31 31 32 32 32 33 33 34 34 35 35 36 36 36 37 37 37 37 38 38 38 38 38 39 9 0 DESIGN APPLICATIONS 9 1 PC AT Floppy Disk Controller 9 1 1 PC AT Floppy Disk Controller Architecture 9 1 2 82077AA PC AT Solution 9 2 3 5 Drive Interfacing 9 2 1 3 5 Drives Under the AT Mode 9 2 2 3 5 Drives Under the PS 2 Modes 9 2 3 Combining 5 25 and 3 5 Drives 10 0 D C SPECIFICATIONS 10 1 Absolute Maximum Ratings 10 2 D C Characteristics 11 0 A C SPECIFICATIONS 12 0 DATA SEPARATOR CHARACTERISTICS FOR FLOPPY DISK MODE 13 0 DATA SEPARATOR CHARACTERISTICS FOR TAPE DRIVE MODE 14 0 82077AA 68-LEAD PLCC PACKAGE THERMAL CHARACTERISTICS 15 0 REVISION SUMMARY 60 61 61 62 3 82077AA Table 1 82077AA Pin Description Symbol Pin I O Description HOST INTERFACE RESET CS A0 A1 A2 32 6 7 8 10 I I I RESET A high level places the 82077AA in a known idle state All registers are cleared except those set by the Specify command CHIP SELECT Decodes base address range and qualifies RD and WR inputs ADDRESS Selects one of the host interface registers A2 A1 A0 0 0 0 0 1 1 1 1 1 1 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 RD WR DRQ 11 13 14 15 17 19 20 22 4 5 24 0 0 1 1 0 0 0 1 1 1 Register 0 R Status Register A 1 R Status Register B 0 R W Digital Output Register 1 R W Tape Drive Register 0 R Main Status Register 0 W Data Rate Select Register 1 R W Data (FIFO) 0 Reserved 1 R Digital Input Register 1 W Configuration Control Register I O DATA BUS Data bus with 12 mA drive I I READ Control signal WRITE Control signal O DMA REQUEST Requests service from a DMA controller Normally active high but goes to high impedance in AT and Model 30 modes when the appropriate bit is set in the DOR I DMA ACKNOWLEDGE Control input that qualifies the RD WR inputs in DMA cycles Normally active low but is disabled in AT and Model 30 modes when the appropriate bit is set in the DOR TERMINAL COUNT Control line from a DMA controller that terminates the current disk transfer TC is accepted only while DACK is active This input is active high in the AT and Model 30 modes and active low in the PS 2 mode DACK 3 TC 25 I INT 23 O INTERRUPT Signals a data transfer in non-DMA mode and when status is valid Normally active high but goes to high impedance in AT and Model 30 modes when the appropriate bit is set in the DOR CRYSTAL 1 2 Connection for a 24 MHz fundamental mode parallel resonant crystal X1 may be driven with a MOS level clock and X2 would be left unconnected X1 X2 33 34 4 82077AA Table 1 82077AA Pin Description (Continued) Symbol Pin I O Description HOST INTERFACE (Continued) IDENT 27 I IDENTITY Upon Hardware RESET this input (along with MFM pin) selects between the three interface modes After RESET this input selects the type of drive being accessed and alters the level on DENSEL The MFM pin is also sampled at Hardware RESET and then becomes an output again Internal pullups on MFM permit a no connect IDENT 1 1 0 0 MFM 1 or NC 0 1 or NC 0 INTERFACE AT Mode ILLEGAL PS 2 Mode Model 30 Mode AT MODE Major options are enables DMA Gate logic TC is active high Status Registers A B not available PS 2 MODE Major options are No DMA Gate logic TC is active low Status Registers A B are available MODEL 30 MODE Major options are enable DMA Gate logic TC is active high Status Registers A B available After Hardware reset this pin determines the polarity of the DENSEL pin IDENT at a logic level of ‘‘1’’ DENSEL will be active high for high (500 Kbps 1 Mbps) data rates (typically used for 5 25 drives) IDENT at a logic level of ‘‘0’’ DENSEL will be active low for high data rates (typically used for 3 5 drives) INVERT is tied to ground DISK CONTROL (All outputs have 40 mA drive capability) INVERT 35 I INVERT Strapping option Determines the polartity of all signals in this section Should be strapped to ground when using the internal buffers and these signals become active LOW When strapped to VCC these signals become active high and external inverting drivers and receivers are required ME0–3 Decoded Motor enables for drives 0 – 3 The motor enable pins are directly controlled via the Digital Output Register ME0 ME1 ME2 ME3 DS0 DS1 DS2 DS3 HDSEL STEP DIR WRDATA WE 57 61 63 66 58 62 64 67 51 55 56 53 52 O O DRIVE SELECT 0 – 3 Decoded drive selects for drives 0 – 3 These outputs are decoded from the select bits in the Digital Output Register and gated by ME0–3 HEAD SELECT Selects which side of a disk is to be used An active level selects side 1 STEP Supplies step pulses to the drive DIRECTION Controls the direction the head moves when a step signal is present The head moves toward the center if active WRITE DATA FM or MFM serial data to the drive Precompensation value is selectable through software WRITE ENABLE Drive control signal that enables the head to write onto the disk O O O O O 5 82077AA Table 1 82077AA Pin Description (Continued) Symbol Pin I O Description DISK CONTROL (All outputs have 40 mA drive capability) (Continued) DENSEL DSKCHG DRV2 TRK0 WP INDX 49 31 30 2 1 26 O I I I I I DENSITY SELECT Indicates whether a low (250 300 Kbps) or high (500 Kbps 1 Mbps) data rate has been selected DISK CHANGE This input is reflected in the Digital Input Register DRIVE2 This indicates whether a second drive is installed and is reflected in Status Register A TRACK0 Control line that indicates that the head is on track 0 WRITE PROTECT Indicates whether the disk drive is write protected INDEX Indicates the beginning of the track PLL SECTION RDDATA HI