COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER

www.DataSheet4U.com 8XC198 COMMERCIAL EXPRESS CHMOS MICROCONTROLLER 8 Kbytes of OTPROM Y Y Y Y Y Y Y Y Y 8 Kbytes of On-Chip OTPROM or ROM 232 Byte Register File Register-to-Register Architecture 28 Interrupt Sources 16 Vectors 1 75 ms 16 x 16 Multiply (16 MHz) 3 0 ms 32 16 Divide (16 MHz) Powerdown and Idle Modes 16-Bit Watchdog Timer 8-Bit External Bus Y Y Y Y Y Y Y Y Y 16 MHz Standard Full Duplex Serial Port High Speed I O Subsystem 16-Bit Timer 16-Bit Counter Pulse-Width-Modulated Output Four 16-Bit Software Timers 10-Bit A D Converter with Sample Hold Extended Temperature Available The 8XC198 family offers low-cost entry into Intel’s powerful MCS -96 16-bit microcontroller architecture Intel’s CHMOS process provides a high performance processor along with low power consumption To further reduce power requirements the processor can be placed into Idle or Powerdown Mode The 8XC198 is the 8-bit bus version of the 8XC196KB The prefixes mean 80 (ROMless) 83 (ROM) 87 (OTP) One Time Programmable The ROM and OTP are available in 8 Kbytes Bit byte word and some 32-bit operations are available on the 8XC198 With a 16 MHz oscillator a 16-bit addition takes 0 50 ms and the instruction times average 0 37 ms to 1 1 ms in typical applications Four high-speed capture inputs are provided to record times when events occur Six high-speed outputs are available for pulse or waveform generation The high-speed output can also generate four software timers or start an A D conversion Events can be based on the timer or counter Also provided on-chip are an A D converter serial port watchdog timer and a pulse-width-modulated output signal With the commercial (standard) temperature option operational characteristics are guaranteed over the temperature range of 0 C to a 70 C Wth the extended temperature range option operational characteristics are guaranteed over the temperature range of b 40 C to a 85 C MCS -96 is a registered trademark of Intel Corporation Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTEL CORPORATION 1995 October 1992 Order Number 272034-003 8XC198 272034 – 1 Figure 1 87C198 Block Diagram 0FFFFH EXTERNAL MEMORY OR I O 4000H INTERNAL ROM EPROM OR EXTERNAL MEMORY 2080H RESERVED 2040H UPPER 8 INTERRUPT VECTORS 2030H ROM OTP SECURITY KEY 2020H RESERVED 2019H CHIP CONFIGURATION BYTE 2018H RESERVED 2014H LOWER 8 INTERRUPT VECTORS PLUS 2 SPECIAL INTERRUPTS 2000H PORT 3 AND PORT 4 1FFEH EXTERNAL MEMORY OR I O 0100H INTERNAL DATA MEMORY - REGISTER FILE (STACK POINTER RAM AND SFRS) EXTERNAL PROGRAM CODE MEMORY 272034 – 7 Figure 3 Chip Configuration (2018H) 0000H Figure 2 Memory Map WARNING Reserved memory locations must not be written or read The contents and or function of these locations may change with future revisions of the device Therefore a program that relies on one or more of these locations may not function properly 2 8XC198 PACKAGING The 8XC198 is available in a 52-pin PLCC package and an 80-pin QFP package Contact your local sales office to determine the exact ordering code for the part desired Package Designators N e 52-pin PLCC S e 80-pin QFP Thermal Characteristics Package Type PLCC QFP ija 40 C W 70 C W 4C W ijc All thermal impedance data is approximate for static air conditions at 1W of power dissipation Values will change depending on operating conditions and application See the Intel Packaging Handbook (Order Number 240800) for a description of Intel’s thermal impedance test methodology 272034 – 2 Figure 4 52-Pin PLCC Package NOTE The above pinout diagram applies to the OTP (87C198) device The OTP device uses all of the programming pins shown above The ROM (83C198) device only uses programming pins AINC PALE PMODE n and PROG The ROMless (80C198) doesn’t use any of the programming pins 3 8XC198 272034 – 4 NOTE N C means No Connect (do not connect these pins) Figure 5 80-Pin QFP Package NOTE The above pinout diagram applies to the OTP (87C198) device The OTP device uses all of the programming pins shown above The ROM (83C198) device only uses programming pins AINC PALE PMODE n and PROG The ROMless (80C198) doesn’t use any of the programming pins 4 8XC198 PIN DESCRIPTIONS Symbol VCC VSS VREF Main supply voltage (5V) The PLCC package has 5 VSS pins and the QFP package has 12 VSS pins All must be connected to digital ground Reference voltage for the A D converter (5V) VREF is also the supply voltage to the analog portion of the A D converter and the logic used to read Port 0 Must be connected for A D and Port 0 to function Reference ground for the A D converter Must be held at nominally the same potential as VSS Programming Voltage Also timing pin for the return from powerdown circuit Input of the oscillator inverter and of the internal clock generator Output of the oscillator inverter Reset input to and open-drain output from the chip Input low for at least 4 state times to reset the chip The subsequent low-to-high transition commences the 10-state Reset Sequence Output high during an external memory read indicates the read is an instruction fetch INST is valid throughout the bus cycle INST is activated only during external memory accesses and output low for a data fetch Input for memory select (External Access) EA equal to a TTL-high causes memory accesses to locations 2000H through 3FFFH to be directed to on-chip ROM EPROM EA equal to a TTL-low causes accesses to these locations to be directed to off-chip memory Address Latch Enable or Address Valid output as selected by CCR Both pin options provide a latch to demultiplex the address from the address data bus When the pin is ADV it goes inactive high at the end of the bus cycle ALE ADV is activated only during external memory accesses Read signal output to external memory RD is activated only during external memory reads Write output to external memory WR will go low for every external write Ready input to lengthen external memory cycles When the external memory is not being used READY has no effect Internal control of the number of wait states inserted into a bus cycle held not ready is available through configuration of CCR Inputs to High Speed Input Unit Four HSI pins are available HSI 0 HSI 1 HSI 2 and HSI 3 Two of them (HSI 2 and HSI 3) are shared with the HSO Unit Outputs from High Speed Output Unit Six HSO pins are available HSO 0 HSO 1 HSO 2 HSO 3 HSO 4 and HSO 5 Two of them (HSO 4 and HSO 5) are shared with the HSI Unit 4-bit high impedance input-only port These pins can be used as digital inputs and or as analog inputs to the on-chip A D converter These pins set the Programming Mode on the EPROM device Name and Function ANGND VPP XTAL1 XTAL2 RESET INST EA ALE ADV RD WR READY HSI HSO Port 0 5 8XC198 PIN DESCRIPTIONS (Continued) Symbol Port 2 Ports 3 and 4 Name and Function Multi-functional port All of its pins are shared with other functions in the 80C198 8-bit bidirectional I O ports with open drain outputs These pins are shared with the multiplexed address data bus which has strong internal pullups Available as I O only on the ROM and EPROM devices The TxD pin is used for serial port transmission in Modes 1 2 and 3 In mode 0 the pin is used as the serial clock output Serial Port Receive pin used for serial port reception In mode 0 the pin functions as input or output data A positive transition on the EXTINT pin will generate an external interrupt The T2CLK pin is the Timer2 clock input or the serial port baud rate generator input A rising edge on the T2RST pin will reset Timer2 The PWM output Programming Mode Select Determines the EPROM programming algorithm that is performed PMODE is sampled after a chip reset and should be static while the part is operating Slave ID Number Used to assign each slave a pin of Port 3 or 4 to use for passing programming verification acknowledgement Programming ALE Input Accepted by the 87C196KB when it is in Slave Programming Mode Used to indicate that Ports 3 and 4 contain a command address Programming Falling edge indicates valid data on PBUS and the beginning of programming Rising edge indicates end of programming Program Valid This signal indicates the success or failure of programming in the Auto Programming Mode A zero indicates successful programming Program Verification Used in Slave Programming and Auto CLB Programming Modes Signal is low after rising edge of PROG if the programming was not successful Auto Increment Active low signal indicates that the auto increment mode is enabled Auto Increment will allow reading or writing of sequential EPROM locations without address transactions across the PBUS for each read or write Address Command Data Bus Used to pass commands addresses and data to and from slave mode 87C196KBs Used by chips in Auto Programming Mode to pass command addresses and data to slaves Also used in the Auto Programming Mode as a regular system bus to access external memory Should have pullups to VCC (15 kX) TxD RxD EXTINT T2CLK T2RST PWM PMODE SID PALE PROG PVAL PVER AINC PORTS 3 and 4 (when programming) 6 8XC198 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Ambient Temperature under Bias Storage Temperature Voltage on VPP or EA to VSS or ANGND Voltage on Any Other Pin to VSS Power Dissipation(1) b 55 C to a 125 C b 65 C to a 150 C b 0 3V to a 13 0V b 0 5V to a 7 0V NOTICE This data sheet contains preliminary information on new products in production It is valid for the devices indicated in the revision history The specifications are sub