64 Bit Processor

64-bit Intel® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet March 2005 Document Number: 306754-001 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. 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Copyright © 2005, Intel Corporation. 2 64-bit Intel® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet Contents 1 Introduction....................................................................................................................... 11 1.1 1.2 1.3 2 2.1 Terminology......................................................................................................... 12 References .......................................................................................................... 14 State of Data ....................................................................................................... 15 Front Side Bus and GTLREF .............................................................................. 17 2.1.1 Front Side Bus Clock and Processor Clocking....................................... 18 2.1.2 Front Side Bus Clock Select (BSEL[1:0]) ............................................... 19 2.1.3 Phase Lock Loop (PLL) Power and Filter............................................... 19 Voltage Identification (VID).................................................................................. 20 Cache Voltage Identification (CVID).................................................................... 23 Reserved, Unused, and TESTHI Pins.................................................................24 Mixing Processors ............................................................................................... 24 Front Side Bus Signal Groups............................................................................. 25 GTL+ Asynchronous and AGTL+ Asynchronous Signals ................................... 27 Test Access Port (TAP) Connection.................................................................... 27 Maximum Ratings................................................................................................ 27 Processor DC Specifications............................................................................... 28 2.10.1 Flexible Motherboard (FMB) Guidelines................................................. 28 2.10.2 VCC and VCACHE Overshoot Specification.......................................... 32 2.10.3 Die Voltage Validation ............................................................................ 33 AGTL+ Front Side Bus Specifications .................................................................37 Front Side Bus AC Specifications ....................................................................... 37 Processor AC Timing Waveforms ....................................................................... 42 Front Side Bus Signal Quality Specifications and Measurement Guidelines ...... 53 3.1.1 Ringback Guidelines .............................................................................. 53 3.1.2 Overshoot/Undershoot Guidelines ......................................................... 56 3.1.3 Overshoot/Undershoot Magnitude ......................................................... 56 3.1.4 Overshoot/Undershoot Pulse Duration................................................... 57 3.1.5 Activity Factor......................................................................................... 57 3.1.6 Reading Overshoot/Undershoot Specification Tables............................ 57 3.1.7 Determining if a System Meets Over/Undershoot Specifications........... 58 Package Mechanical Drawing ............................................................................. 62 Processor Component Keep-Out Zones ............................................................. 65 Package Loading Specifications ......................................................................... 65 Package Handling Guidelines ............................................................................. 66 Package Insertion Specifications ........................................................................ 66 Processor Mass Specifications ........................................................................... 66 Processor Materials............................................................................................. 66 Processor Markings............................................................................................. 67 Processor Pin-Out Coordinates........................................................................... 68 Electrical Specifications.................................................................................................... 17 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 3 3.1 Front Side Bus Signal Quality Specifications ................................................................... 53 4 Mechanical Specifications ................................................................................................ 61 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 64-bit Intel® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet 3 5 Pin Listing......................................................................................................................... 69 5.1 Processor Pin Assignments ................................................................................ 69 5.1.1 Pin Listing by Pin Name ......................................................................... 69 5.1.2 Pin Listing by Pin Number ...................................................................... 78 Signal Definitions ................................................................................................ 87 Package Thermal Specifications ......................................................................... 97 7.1.1 Thermal Specifications ........................................................................... 97 7.1.2 Thermal Metrology ............................................................................... 100 Processor Thermal Features............................................................................. 100 7.2.1 Thermal Monitor ................................................................................... 100 7.2.2 Thermal Monitor 2 ................................................................................ 101 7.2.3 On-Demand Mode................................................................................ 102 7.2.4 PROCHOT# Signal Pin ........................................................................ 103 7.2.5 FORCEPR# Signal Pin ........................................................................ 103 7.2.6 THERMTRIP# Signal Pin ..................................................................... 103 7.2.7 TCONTROL and Fan Speed Reduction............................................... 103 7.2.8 Thermal Diode...................................................................................... 104 Power-On Configuration Options ...................................................................... 105 Clock Control and Low Power States................................................................ 105 8.2.1 Normal State ........................................................................................ 106 8.2.2 HALT or Enhanced Power Down State ................................................ 106 8.2.3 Stop-Grant State .................................................................................. 107 8.2.4 Enhanced HALT Snoop State or HALT Snoop State, Stop Grant Snoop State ....................................................................... 108 Enhanced Intel SpeedStep® Technology.......................................................... 108 System Management Bus (SMBus) Interface ................................................... 109 8.4.1 Processor Information ROM (PIROM).................................................. 110 8.4.2 Scratch EEPROM ................................................................................ 112 8.4.3 PIROM and Scratch EEPROM Supported SM