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Motorola
Motorola

74LS95 Datasheet

4-BIT SHIFT REGISTER


74LS95 Datasheet Preview


4-BIT SHIFT REGISTER
The SN54/74LS95B is a 4-Bit Shift Register with serial and parallel
synchronous operating modes. The serial shift right and parallel load are acti-
vated by separate clock inputs which are selected by a mode control input.
The data is transferred from the serial or parallel D inputs to the Q outputs
synchronous with the HIGH to LOW transition of the appropriate clock input.
The LS95B is fabricated with the Schottky barrier diode process for high
speed and is completely compatible with all Motorola TTL families.
Synchronous, Expandable Shift Right
Synchronous Shift Left Capability
Synchronous Parallel Load
Separate Shift and Load Clock Inputs
Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC Q0
14 13
Q1 Q2
12 11
Q3 CP1 CP2
10 9
8
NOTE:
The Flatpak version has the
same pinouts (Connection
Diagram) as the Dual In-Line
Package.
1234567
DS P0 P1 P2 P3 S GND
VCC = PIN 14
GND = PIN 7
PIN NAMES
LOADING (Note a)
HIGH
LOW
S
DS
P0 – P3
CP1
CP2
Q0 – Q3
Mode Control Input
Serial Data Input
Parallel Data Inputs
Serial Clock (Active LOW Going Edge) Input
Parallel Clock (Active LOW Going Edge) Input
Parallel Outputs (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.
SN54/74LS95B
4-BIT SHIFT REGISTER
LOW POWER SCHOTTKY
14
1
J SUFFIX
CERAMIC
CASE 632-08
14
1
N SUFFIX
PLASTIC
CASE 646-06
14
1
D SUFFIX
SOIC
CASE 751A-02
ORDERING INFORMATION
SN54LSXXJ
SN74LSXXN
SN74LSXXD
Ceramic
Plastic
SOIC
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA Operating Ambient Temperature Range
IOH Output Current — High
IOL Output Current — Low
Min Typ Max Unit
54 4.5 5.0 5.5
74 4.75 5.0 5.25
V
54 – 55 25 125 °C
74 0 25 70
54, 74
– 0.4
mA
54 4.0 mA
74 8.0
FAST AND LS TTL DATA
5-171
Page 1

SN54 / 74LS95B
6
S
1
DS
LOGIC DIAGRAM
P0 P1
23
P2
4
P3
5
9
CP1
8
CP2
R RRR
VCC = PIN 14
GND = PIN 7
= PIN NUMBERS
SQ
13
Q0
FUNCTIONAL DESCRIPTION
The LS95B is a 4-Bit Shift Register with serial and parallel
synchronous operating modes. It has a Serial (DS) and four
Parallel (P0 – P3) Data inputs and four Parallel Data outputs
(Q0 – Q3). The serial or parallel mode of operation is controlled
by a Mode Control input (S) and two Clock Inputs (CP1) and
(CP2). The serial (right-shift) or parallel data transfers occur
synchronous with the HIGH to LOW transition of the selected
clock input.
When the Mode Control input (S) is HIGH, CP2 is enabled. A
HIGH to LOW transition on enabled CP2 transfers parallel
data from the P0 – P3 inputs to the Q0 – Q3 outputs.
When the Mode Control input (S) is LOW, CP1 is enabled. A
SQ
12
Q1
SQ
11
Q2
SQ
10
Q3
HIGH to LOW transition on enabled CP1 transfers the data
from Serial input (DS) to Q0 and shifts the data in Q0 to Q1, Q1
to Q2, and Q2 to Q3 respectively (right-shift). A left-shift is ac-
complished by externally connecting Q3 to P2, Q2 to P1, and
Q1 to P0, and operating the LS95B in the parallel mode (S =
HIGH).
For normal operation, S should only change states when
both Clock inputs are LOW. However, changing S from LOW
to HIGH while CP2 is HIGH, or changing S from HIGH to LOW
while CP1 is HIGH and CP2 is LOW will not cause any changes
on the register outputs.
MODE SELECT — TRUTH TABLE
OPERATING MODE
INPUTS
OUTPUTS
S CP1 CP2 DS Pn Q0 Q1 Q2 Q3
Shift
Parallel Load
L X I X L q0 q1 q2
L X h X H q0 q1 q2
HX
X Pn P0 P1 P2 P3
Mode Change
L L XX
L L XX
H L XX
H L XX
L H XX
L H XX
H H XX
H H XX
No Change
No Change
No Change
Undetermined
Undetermined
No Change
Undetermined
No Change
L = LOW Voltage Level
H = HIGH Voltage Level
X = Don’t Care
I = LOW Voltage Level one set-up time prior to the HIGH to LOW clock transition.
h = HIGH Voltage Level one set-up time prior to the HIGH to LOW clock transition.
Pn = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the Pn
= HIGH to LOW clock transition.
FAST AND LS TTL DATA
5-172
Page 2

SN54 / 74LS95B
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VIH Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
54 0.7 Guaranteed Input LOW Voltage for
VIL Input LOW Voltage 74 0.8 V All Inputs
VIK
VOH
Input Clamp Diode Voltage
Output HIGH Voltage
– 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
54 2.5 3.5
74 2.7 3.5
V VCC = MIN, IOH = MAX, VIN = VIH
V or VIL per Truth Table
VOL
Output LOW Voltage
54, 74
74
0.25 0.4
0.35 0.5
V IOL = 4.0 mA
V IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
IIH Input HIGH Current
20 µA VCC = MAX, VIN = 2.7 V
0.1 mA VCC = MAX, VIN = 7.0 V
IIL Input HIGH Current
– 0.4 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1)
– 20 –100 mA VCC = MAX
ICC Power Supply Current
21 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Symbol
fMAX
tPLH
tPHL
Parameter
Maximum Clock Frequency
CP to Output
Limits
Min Typ Max
25 36
18 27
21 32
Unit
MHz
ns
ns
Test Conditions
VCC = 5.0 V
CL = 15 pF
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Symbol
tW
ts
th
ts
th
Parameter
CP Pulse Width
Data Setup Time
Data Hold Time
Mode Control Setup Time
Mode Control Hold Time
Limits
Min Typ Max
20
20
20
20
20
Unit
ns
ns
ns
ns
ns
Test Conditions
VCC = 5.0 V
FAST AND LS TTL DATA
5-173
Page 3

SN54 / 74LS95B
DESCRIPTION OF TERMS
SETUP TIME(ts) —is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from HIGH to LOW in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from HIGH to LOW that the logic level must
be maintained at the input in order to ensure continued recog-
nition. A negative HOLD TIME indicates that the correct logic
level may be released prior to the clock transition from HIGH to
LOW and still be recognized.
AC WAVEFORMS
The shaded areas indicate when the input is permitted to change for predictable output performance.
D
CP1 or CP2
Q
1.3 V
1.3 V
th(L)
ts(L)
1.3 V
1.3 V
tPHL
l/fmax
1.3 V
1.3 V 1.3 V
ts(H)
1.3 V
tW
th(H)
*The Data Input is
(DS for CP1) or (Pn for CP2).
tPLH
1.3 V
Figure 1
(H L ONLY)
S 1.3 V
(L H ONLY)
1.3 V
(L H ONLY)
STABLE
ts(H)
ts(L)
th(L)
ts(L)
ts(H)
th(LĂORĂH)
CP1
1.3 V
CP2
1.3 V
1.3 V
tW
ts(L)
ts(H)
th(H)
1.3 V
1.3 V
1.3 V
tW
1.3 V
1.3 V
Figure 2
FAST AND LS TTL DATA
5-174
Page 4
Part Number 74LS95
Manufactur Motorola
Description 4-BIT SHIFT REGISTER
Total Page 6 Pages
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