OCTAL D-TYPE FLIP-FLOP WITH CLEAR

SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR SDLS090 – OCTOBER 1976 – REVISED MARCH 1988 • • • • Contains Eight Flip-Flops With Single-Rail Outputs Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators SN54273, SN74LS273 . . . J OR W PACKAGE SN74273 . . . N PACKAGE SN74LS273 . . . DW OR N PACKAGE (TOP VIEW) description These monolithic, positive-edge-triggered flipflops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear input. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect ar the output. These flip-flops are guaranteed to respond to clock frequencies ranging form 0 to 30 megahertz while maximum clock frequency is typically 40 megahertz. Typical power dissipation is 39 milliwatts per flip-flop for the ′273 and 10 milliwatts for the ′LS273. CLR 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK SN54LS273 . . . FK PACKAGE (TOP VIEW) 2D 2Q 3Q 3D 4D 4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13 1D 1Q CLR V CC 8Q 8D 7D 7Q 6Q 6D FUNCTION TABLE (each flip-flop) INPUTS CLEAR L H H H CLOCK X ↑ ↑ L D X H L X OUTPUT Q L H L Q0 logic symbol† CLR CLK 1D 2D 3D 4D 5D 6D 7D 8D 1 11 3 4 7 8 13 14 17 18 EN C1 1D 2 5 6 9 12 15 16 19 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q † This symbol is in accordance with ANSI/IEEE Std. 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW, J, N, and W packages. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1988, Texas Instruments Incorporated POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4Q GND CLK 5Q 5D 1 SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR SDLS090 – OCTOBER 1976 – REVISED MARCH 1988 schematics of inputs and outputs ′273 EQUIVALENT OF EACH INPUT VCC Req 100 Ω NOM TYPICAL OF ALL OUTPUTS VCC INPUT OUTPUT Clear: Req = 3 kΩ NOM Clock: Req = 6 kΩ NOM All other inputs: Req = 8 kΩ NOM ′LS273 EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS VCC 120 Ω NOM VCC 20 kΩ NOM INPUT OUTPUT logic diagram (positive logic) 1D CLOCK 11 3 2D 4 3D 7 4D 8 5D 13 6D 14 7D 17 8D 18 1D C1 R 1 2 1Q 1D C1 R 1D C1 R 1D C1 R 1D C1 R 1D C1 R 1D C1 R 1D C1 R CLEAR 5 2Q 6 3Q 9 4Q 12 5Q 15 6Q 16 7Q 19 8Q Pin numbers shown are for the DW, J, N, and W packages. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR SDLS090 – OCTOBER 1976 – REVISED MARCH 1988 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA: SN54273 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C SN74273 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54273 MIN Supply voltage, VCC High-level output current, IOH Low-level output current, IOL Clock frequency, fclock Width of clock or clear pulse, tw Setup time tsu time, Data hold time, th Operating free-air temperature, TA ↑ The arrow indicates that the rising edge of the clock pulse is used for reference. Data input Clear inactive state 0 16.5 20↑ 25↑ 5↑ – 55 125 4.5 NOM 5 MAX 5.5 – 800 16 30 0 16.5 20↑ 25↑ 5↑ 0 70 MIN 4.75 SN74273 NOM 5 MAX 5.25 – 800 16 30 UNIT V µA mA MHz ns ns ns °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH VIL VIK VOH VOL II IIH IIL High-level input voltage Low-level input voltage Input clamp voltage High-level output voltage Low-level output voltage Input current at maximum input voltage High-level High level input current Low-level Low level input current Clear Clock or D Clear Clock or D VCC = MIN, VCC = MIN, VIL = 0.8 V, VCC = MIN, VIL = 0.8 V, VCC = MAX, VCC = MAX MAX, VCC = MAX MAX, II = – 12 mA VIH = 2 V, IOH = – 800 µA VIH = 2 V, IOH = 16 mA VI = 5.5 V VI = 2 4 V 2.4 VI = 0 4 V 0.4 TEST CONDITIONS† MIN 2 0.8 –1.5 2.4 3.4 0.4 1 80 40 – 3.2 – 1.6 TYP‡ MAX UNIT V V V V V mA µA mA IOS Short-circuit output current§ VCC = MAX – 18 – 57 mA ICC Supply current VCC = MAX, See Note 2 62 94 mA † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time. NOTE 2: With all outputs open and 4.5 V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5 V, is applied to clock. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR SDLS090 – OCTOBER 1976 – REVISED MARCH 1988 switching characteristics, VCC = 5 V, TA = 25°C PARAMETER fmax tPHL tPLH tPHL Maximum clock frequency Propagation delay time, high-to-low-level output from clear Propagation delay time, low-to-high-level output from clock Propagation delay time, high-to-low-level output from clock CL = 15 pF, Ω, RL = 400 Ω See Note 3 TEST CONDITIONS MIN 30 TYP 40 18 17 18 27 27 27 MAX UNIT MHz ns ns ns NOTE 3: Load circuits and voltage waveforms are shown in Section 1. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating free-air temperature range, TA: SN54LS273 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C SN74LS273 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54LS273 MIN Supply voltage, VCC High-level output current, IOH Low-level output current, IOL Clock frequency, fclock Width of clock or clear pulse, tw Setup time tsu time, Data hold time, th Operating free-air temperature, TA ↑ The arrow indicates that the rising edge of the clock pulse is used for reference. Data input Clear inactive state 0 20 20↑ 25↑ 5↑ – 55 125 4.5 NOM 5 MAX 5.5 – 400 4 30 0 20 20↑ 25↑ 5↑ 0 70 SN74LS273 MIN 4.75 NOM 5 MAX 5.25 – 400 8 30 UNIT V µA mA MHz ns ns ns °C 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR SDLS090 – OCTOBER 1976 – REVISED MARCH 1988 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH VIL VIK VOH VOL II IIH IIL IOS High-level input voltage Low-level input voltage Input clamp voltage High-level output voltage Low-level Low level output voltage Input current at maximum input voltage High-level input current Low-level input current Short-circuit output current§ VCC = MIN, VCC = MIN, VIL = VILmax, , VCC = MIN, VIL = VILmax, VCC = MAX, VCC = MAX, VCC = MAX, VCC = MAX II = – 18 mA VIH = 2 V, IOH = – 400 µA , VIH = 2 V, IOL = 4 mA IOL = 8 mA TEST CONDITIONS† MIN 2 0.7 –1.5 2.5 3.4 0.25 0.4 2.7 3.4 0.25 0.35 0.1 20 – 0.4 – 20 – 100 – 20 0.4 0.5 0.1 20 – 0.4 – 100 SN54LS273 TYP‡ MAX MIN 2 0.8 –1.5 SN74LS273 TYP‡ MAX UNIT V V V V V mA µA mA mA VI = 7 V VI = 2.7 V VI = 0.4 V ICC Supply current VCC = MAX, See Note 2 17 27 17 27 mA † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time and duration of short circuit should not exceed one second. NOTE 2: With all outputs open and 4.5 V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5 V, is applied to clock. switching characteristics, VCC = 5 V, TA = 25°C PARAMETER fmax tPHL tPLH tPHL Maximum clock frequency Propagation delay time, high-to-low-level output from clear Propagation delay time, low-to-high-level output from clock Propagation delay time, high-to-low-level output from clock CL = 15 pF, kΩ, RL = 2 kΩ See Note 3 TEST CONDITIONS MIN 30 TYP 40 18 17 18 27 27 27 MAX UNIT MHz ns ns ns NOTE 3: Load circuits and voltage waveforms are shown in Section 1. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or s