DM54LS107A DM74LS107A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
June 1989
DM54LS107A DM74LS107A Dual Negative-EdgeTriggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
General Description
This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs The J and K data is processed by the flip-flops on the falling edge of the clock pulse The clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse The data on the J and K inputs may change while the clock is high or low without affecting the outputs as long as setup and hold times are not violated A low logic level on the clear input will reset the outputs regardless of the logic levels of the other inputs
Connection Diagram
Dual-In-Line Package
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TL F 6367 – 1
Order Number DM54LS107AJ DM54LS107AW DM74LS107AM or DM74LS107AN See NS Package Number J14A M14A N14A or W14B
Function Table
Inputs CLR L H H H H H CLK X J X L H L H X K X L L H H X Q L Q0 H L Toggle Q0 Q0 Outputs Q H Q0 L H
v v v v
H
H e High Logic Level X e Either Low or High Logic Level L e Low Logic Level
v e Negative going edge of pulse
Q0 e The output logic level before the indicated input conditions were established Toggle e Each output changes to the complement of its previous level on each falling edge of the clock pulse
C1995 National Semiconductor Corporation
TL F 6367
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings (Note)
If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage Input Voltage 7V 7V Note The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation
Operating Free Air Temperature Range b 55 C to a 125 C DM54LS DM74LS 0 C to a 70 C Storage Temperature Range
b 65 C to a 150 C
Recommended Operating Conditions
Symbol VCC VIH VIL IOH
OL
Parameter Min Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current 45 2
DM54LS107A Nom 5 Max 55 Min 4 75 2 07
b0 4
DM74LS107A Nom 5 Max 5 25
Units V V 08
b0 4
V mA mA MHz MHz ns
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fCLK fCLK tW tW tSU tSU tH tH TA Clock Frequency (Note 2) Clock Frequency (Note 3) Pulse Width (Note 2) Pulse Width (Note 3) Setup Time (Notes 1 Setup Time (Notes 1 Hold Time (Notes 1 Hold Time (Notes 1 Clock High Clear Low Clock High Clear Low 2) 3) 2) 3) 0 0 20 25 25 30 20v 25v 0v 5v
b 55
4 30 25 0 0 20 25 25 30 20v 25v 0v 5v 125 0
8 30 25
ns ns ns ns ns 70 C
Free Air Operating Temperature
Note 1 The symbol (
v) indicates the falling edge of the clock pulse is used for reference
Note 2 CL e 15 pF RL e 2 kX TA e 25 C and VCC e 5V Note 3 CL e 50 pF RL e 2 kX TA e 25 C and VCC e 5V
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol VI VOH Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Conditions VCC e Min II e b18 mA VCC e Min IOH e Max VIL e Max VIH e Min VCC e Min IOL e Max VIL e Max VIH e Min IOL e 4mA VCC e Min II Input Current Input Voltage Max VCC e Max VI e 7V DM54 DM74 DM54 DM74 DM74 J K Clear Clock 25 27 34 34 0 25 0 35 0 25 04 05 04 01 03 04 mA V Min Typ (Note 1) Max
b1 5
Units V V
VOL
2
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) (Continued) Symbol IIH Parameter High Level Input Current Conditions VCC e Max VI e 2 7V J K Clear Clock IIL Low Level Input Current VCC e Max VI e 0 4V J K Clear Clock IOS ICC Short Circuit Output Current Supply Current VCC e Max (Note 2) DM54 DM74
b 20 b 20
Min
Typ (Note 1)
Max 20 60 80
b0 4 b0 8 b0 8 b 100 b 100
Units
mA
mA
mA mA
VCC e Max (Note 3)
4
6
Switching Characteristics at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load)
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fMAX tPLH tPHL tPLH tPHL tPLH tPHL Parameter From (Input) To (Output) RL e 2 kX CL e 15 pF Min Maximum Clock Frequency Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Preset to Q Preset to Q Clear to Q Clear to Q Clock to Q or Q Clock to Q or Q 30 20 20 20 20 20 20 Max CL e 50 pF Min 25 24 28 24 28 24 28 Max MHz ns ns ns ns ns ns Units
Note 1 All typicals are at VCC e 5V TA e 25 C Note 2 Not more than one output should be shorted at a time and the duration should not exceed one second For devices with feedback from the outputs where shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where VO e 2 25V and 2 125V for DM54 and DM74 series respectively with the minimum and maximum limits reduced by one half from their stated values This is very useful when using automatic test equipment Note 3 With all inputs open ICC is measured with the Q and Q outputs high in turn At the time of measurement the clock is grounded
3
Physical Dimensions inches (millimeters)
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14-Lead Ceramic Dual-In-Line Package (J) Order Number DM54LS107AJ NS Package Number J14A
4
Physical Dimensions inches (millimeters) (Continued)
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14-Lead Small Outline Molded Package (M) Order Number DM74LS107AM NS Package Number M14A
14-Lead Molded Dual-In-Line Package (N) Order Number DM74LS107AN NS Package Number N14A
5
DM54LS107A DM74LS107A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
Physical Dimensions inches (millimeters) (Continued)
14-Lead Ceramic Flat Package (W) Order Number DM54LS107AW NS Package Number W14B
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