CGS74C2525 CGS74CT2525 CGS74C2526 CGS74CT2526 1-to-8 Minimum Skew Clock Driver
September 1995
CGS74C2525 CGS74CT2525 CGS74C2526 CGS74CT2526 1-to-8 Minimum Skew Clock Driver
The CGS ’C CT2525 is a minimum skew clock driver with one input driving eight outputs specifically designed for signal generation and clock distribution applications The ’2525 is designed to distribute a single clock to eight separate receivers with low skew across all outputs during both the tPLH and tPHL transitions The ’2526 is similar to the ’2525 but contains a multiplexed clock input to allow for systems with dual clock speeds or systems where a separate test clock has been implemented
Features
Y Y Y Y Y Y Y Y
Y
These CGS devices implement National’s FACTTM family Ideal for signal generation and clock distribution Guaranteed pin to pin and part to part skew Multiplexed clock input (’2526) Guaranteed 2 kV minimum ESD protection Symmetric output current drive of 24 mA for IOL IOH ’CT has TTL-compatible inputs These products are identical to 74AC ACT2525 and 2526 Available as Mil Aero versions 54AC ACT2525 54AC ACT2526
Logic Symbols
’2525
Connection Diagrams
Pin Assignment for DIP and SOIC ’2525
TL F 10684 – 1
’2526
TL F 10684 – 3
’2526
TL F 10684 – 2
TL F 10684 – 4
TRI-STATE is a registered trademark of National Semiconductor Corporation FACTTM is a trademark of National Semiconductor Corporation C1996 National Semiconductor Corporation TL F 10684 RRD-B30M106 Printed in U S A
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Functional Description
On the multiplexed clock device the SEL pin is used to determine which CLKn input will have an active effect on the outputs of the circuit When SEL e 1 the CLK1 input is selected and when SEL e 0 the CLK0 input is selected The non-selected CLKn input will not have any effect on the logical output level of the circuit The output pins act as a single entity and will follow the state of the CLK or CLK1 CLK0 pins when either the multiplexed (’2526) or the straight (’2525) clock distribution chip is selected Pin Description Pin Names CLK CLK0 CLK1 O0 – O7 SEL Description Clock Input (’2525) Clock Inputs (’2526) Outputs Clock Select (’2526)
Truth Tables
’2525 Inputs CLK L H Outputs O0 –O7 L H ’2526 Inputs CLK0 L H X X CLK1 X X L H SEL L L H H Outputs O0 –O7 L H L H
L e Low Voltage Level H e High Voltage Level X e Immaterial
’2525
’2526
TL F 10684–7
TL F 10684 – 8
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Absolute Maximum Ratings (Note 1)
If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (VCC) DC Input Diode Current (IIK) VI e b0 5V VI e VCC a 0 5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO e 0 5V VO e VCC a 0 5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (iJA) Plastic (N) 14-Lead Plastic (M) 14-Lead Plastic (N) 16-Lead Plastic (M) 16-Lead
b 0 5V to a 7 0V b 20 mA a 0 2 mA b 0 5V to (VCC a 0 5V) b 20 mA a 20 mA b 0 5V to (VCC a 0 5V)
g 50 mA g 50 MA
Recommended Operating Conditions
Supply Voltage (VCC) ‘C’ ‘CT’ Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) CGS74C CT 54AC ACT Input Rise and Fall Times Devices (30% to 70% of VCC) VCC e 3 3V 4 5V 5 5V Input Rise and Fall Times Devices (0 8V to 2 0V) 2 0V to 6 0V 4 5V to 5 5V 0V to VCC 0V to VCC
b 40 C to a 85 C b 55 C to a 125 C
10 5 ns max 14 4 ns max 17 6 ns max 9 6 ns max
b 65 C to a 150 C
102 128 97 124
C C C C
W W W W
Note 1 Absolute maximum ratings are those values beyond which damage to the device may occur The databook specifications should be met without exception to ensure that the system design is reliable over its power supply temperature and output input loading variables National does not recommend operation of CGS circuits outside databook specifications
DC Electrical Characteristics for CGS74C and 54AC Family Devices
Over recommended operating conditions unless specified otherwise CGS74C Symbol Parameter VCC (V) TA e a 25 C Typ VIH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage (Note 2) 30 45 55 30 45 55 30 45 55 30 45 55 VOL Maximum Low Level Output Voltage (Note 2) 30 45 55 30 45 55 0 002 0 001 0 001 15 2 25 2 75 15 2 25 2 75 2 99 4 49 5 49 21 3 15 3 85 09 1 35 1 65 29 44 54 2 56 3 86 4 86 01 01 01 0 36 0 36 0 36 54AC TA e b 55 C to a 125 C CGS74C TA e b 40 C to a 85 C Units Conditions
Guaranteed Limits 21 3 15 3 85 09 1 35 1 65 29 44 54 24 37 47 01 01 01 0 40 0 50 0 50 21 3 15 3 85 09 1 35 1 65 29 44 54 2 46 3 76 4 76 01 01 01 0 44 0 44 0 44 V VOUT e 0 1V or VCC b0 1V VOUT e 0 1V or VCC b0 1V IOUT e b50 mA V VIN e VIL or VIH b 12 mA b 24 mA IOH b 24 mA IOUT e 50 mA V VIN e VIL or VIH 12 mA 24 mA IOL 24 mA
VIL
V
VOH
V
V
3
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DC Electrical Characteristics for CGS74C and 54AC Family Devices (Continued)
Over recommended operating conditions unless specified otherwise CGS74C Symbol Parameter VCC (V) TA e a 25 C Typ IIN Maximum Input Leakage Current (Note 3) Minimum Dynamic Output Current (Note 4) Maximum Quiescent Supply Current (Note 3) 55 55 55
g0 1
54AC TA e b 55 C to a 125 C
CGS74C TA e b 40 C to a 85 C Units Conditions
Guaranteed Limits
g1 0 g1 0
mA mA mA mA
VI e VCC GND VOLD e 1 65V Max VOHD e 3 85V Min VIN e VCC or GND
IOLD IOHD ICC
50
b 50
75
b 75
55
80
80 0
80 0
DC Electrical Characteristics for CGS74CT and 54ACT Family Devices
Over recommended operating conditions unless specified otherwise CGS74CT Symbol Parameter VCC (V) TA e a 25 C Typ VIH VIL VOH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage (Note 2) 45 55 45 55 45 55 45 55 VOL Maximum Low Level Output Voltage (Note 2) 45 55 45 55 IIN ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum ICC Input Minimum Dynamic Output Current (Note 4) Maximum Quiescent Supply Current (Note 5) 55 55 55 55 06 0 001 0 001 15 15 15 15 4 49 5 49 20 20 08 08 44 54 3 86 4 86 01 01 0 36 0 36
g0 1
54ACT TA e b 55 C to a 125 C
CGS74CT TA e b 40 C to a 85 C Units Conditions
Guaranteed Limits 20 20 08 08 44 54 3 70 4 70 01 01 0 50 0 50
g1 0
20 20 08 08 44 54 3 76 4 76 01 01 0 44 0 44
g1 0
V V V
VOUT e 0 1V or VCC b0 1V VOUT e 0 1V or VCC b0 1V IOUT e b50 mA VIN e VIL or VIH b 24 mA IOH b 24 mA IOUT e 50 mA VIN e VIL or VIH 24 mA IOL 24 mA VI e VCC GND VI e VCC b 2 1V VOLD e 1 65V Max VOHD e 3 85V Min VIN e VCC or GND
V
V
V
mA mA mA mA
16 50
b 50
15 75
b 75
55
80
160 0
80 0
mA
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AC Electrical Characteristics
Over recommended operating conditions unless specified otherwise CGS74C 54AC TA e b55 C to a 125 C CL e 50 pF Min 30 25 Max 11 0 82 CGS74C TA e b40 C to a 85 C CL e 50 pF Min 30 29 30 33 30 35 15 10 15 10 15 Typ Max 12 5 81 14 0 86 15 0 95 600 ps 500 600 ps 500 ns ns ns Units
Symbol
Parameter
VCC Range (V) (Note 6) 33 50 33 50 33 50 33 50 33 50
TA e a 25 C CL e 50 pF Min Typ 65 50 70 55 80 65 03 02 03 02 Max 11 0 78 13 0 78 14 0 85
tPLH tPHL tPLH tPHL tPLH tPHL tOSHL
Propagation Delay CLK to On (’2525) Propagation Delay CLKn to On (’2526) Propagation Delay SEL to On (’2526) Maximum Skew Common Edge Output-to-Output (Note 7) Variation Maximum Skew Common Edge Output-to-Output (Note 7) Variation Maximum Skew Opposite Edge Output-to-Output (Note 7) Variation Maximum Skew Part-to-Part Variation (Note 8) ’C2525 ’CT2525 ’C2526 ’CT2526
30 32 30 36 30 40
tOSLH
tOST
50
04
10 10
10
ns
tPV
50 50 50
35 50 30
40
ns ns
trise tfall trise tfall
Maximum Rise Fall Time (20% to 80% VCC) Maximum Rise Fall Time (0 8V 2 0V and 2 0V 0 8V)
40
3 75
ns
09
11
ns
AC Electrical Characteristics Over recommended operating conditions unless specified otherwise
CGS74CT Symbol Parameter VCC Range (V) (Note 6) Min tPLH tPHL tPLH tPHL Propagation Delay CLK to On (’2525) Propagation Delay CLKn to On (’2526) 50 50 46 58 TA e a 25 C CL e 50 pF Typ 65 85 Max 90 11 1 54ACT TA e b55 C to a 125 C CL e 50 pF Min Max CGS74CT TA e b40 C to a 85 C CL e 50 pF Min 40 51 Max 10 1 12 4 ns ns Units
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AC Electrical Characteristics
Over recommended operating conditions unless specified otherwise (Continued) CGS74CT Symbol Parameter VCC Range (V) (Note 6) Min tPLH tPHL tOSHL Propagation Delay SEL to On (’2526) Maximum Skew Common Edge Output-to-Output (Note 7) Variation Maximum Skew Common Edge Output-to-Output (Note 7) Variation Maximum Skew Opposite Edge Output-to-Output (Note 7) Variation Maximum Skew Part-to-Part Variation (Note 8) AC2525 ACT2525 AC2526 ACT2526 trise tfall trise tfall Maximum Rise Fall Time (20% to 80% VCC) Maximum Rise Fall Time (0 8V 2 0V and 2 0V 0 8V) 50 51 TA e a 25 C CL e 50 pF Typ 85 Max 12 4 54ACT TA e b55 C to a 125 C CL e 50 pF Min Max CGS74CT TA e b40 C to a 85 C CL e 50 pF Min 44 Typ Max 14 1 ns Units
50
02
550
ps
tOSLH
50
02
550
ps
tOST
50
04
10
ns
tPV
50 50 50
35 50 30 3 75
ns ns ns
09
11
ns
Note 2 All outputs loaded thresholds on input associated with output under test Note 3 IIN and ICC ICC for 54AC Note 5 ICC for 54ACT 3 0V are guaranteed to be less than or equal to the respective limit 25 C is identical to CGS74C 25 C is identical to CGS74CT 25 C 25 C 5 5V VCC
Note 4 Maximum test duration 2 0 ms one output loaded at a time Note 6 Voltage Range 5 0 is 5 0V g 0 5V voltage range 3 3 is 3 3V g 0 3V Note 7 Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device The specifications apply to any outputs switching in the same direction either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH) or in opposite directions both HL and LH (tOST) tOSHL and tOSLH are characterized and guaranteed by design 1 MHz Note 8 Part
