OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING

74AC373 OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING s s s s s s (OE). While the LE inputs is held at a high level, the Q outputs will follow the data input precisely or s inversely. When the LE is taken low, the Q outputs will be latched precisely or inversely at s the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic DESCRIPTION state (high or low logic level) and while high level The AC373 is an advanced high-speed CMOS the www.DataSheet4U.comoutputs will be in a high impedance state. OCTAL D-TYPE LATCH with 3 STATE OUTPUT This device is designed to interface directly High NON INVERTING fabricated with sub-micron Speed CMOS systems with TTL and NMOS 2 silicon gate and double-layer metal wiring C MOS components. technology. It is ideal for low power applications All inputs and outputs are equipped with mantaining high speed operation similar to protection circuits against static discharge, giving equivalent Bipolar Schottky TTL. them 2KV ESD immunity and transient excess These 8 bit D-Type latch are controlled by a latch voltage. enable input (LE) and an output enable input s HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 8 µA (MAX.) at TA = 25 oC HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373 IMPROVED LATCH-UP IMMUNITY B M (Plastic Package) (Micro Package) ORDER CODES : 74AC373B 74AC373M PIN CONNECTION AND IEC LOGIC SYMBOLS April 1997 1/10 74AC373 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 11 10 20 SYMBOL OE Q0 to Q7 NAME AND F UNCTIO N 3 State Output Enable Input (Active LOW) Data Inputs D0 to D7 3 State Outputs LE GND VCC Latch Enable Input Ground (0V) Positive Supply Voltage TRUTH TABLE INPUT S OE H L L L LE X L H H D X X L H OUT PUT S Q Z NO CHANGE L H X: DON’T CARE Z: HIGH IMPEDANCE *: Q OUTPUTS ARE LATCHED AT THE TIME WHEN THE INPUT IS TAKEN LOW LOGIC LEVEL. LOGIC DIAGRAMS 2/10 74AC373 ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 ± 20 ± 20 ± 50 ± 400 -65 to +150 300 Unit V V V mA mA mA mA o o ICC or IGND DC VCC or Ground Current C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO Top dt/dv Supply Voltage Input Voltage Output Voltage Operating Temperature: Input Rise and Fall Time VCC = 3.0, 4.5 or 5.5 V(note 1) Parameter Value 2 to 6 0 to VCC 0 to VCC -40 to +85 8 Un it V V V o C ns/V 1) VIN from 30% to 70% of VCC 3/10 74AC373 DC SPECIFICATIONS Symbol Parameter V CC (V) VIH High Level Input Voltage 3.0 4.5 5.5 VIL Low Level Input Voltage 3.0 4.5 5.5 VOH High Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 VOL Low Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 II IOZ Input Leakage Current 3-State Output Off-state Current Quiescent Supply Current Dynamic Output Current (note 1, 2) 5.5 5.5 V I (*) = V IH or V IL VI = V IH or V IL (*) Test Con dition s Min. VO = 0.1 V or VCC - 0.1 V VO = 0.1 V or VCC - 0.1 V I O=-50 µA IO=-50 µA IO=-50 µA IO=-12 mA IO=-24 mA IO=-24 mA IO=50 µA IO=50 µA IO=50 µA IO=12 mA IO=24 mA IO=24 mA VI = VCC or GND VI = VCC or GND VO = VCC or GND VI(OE) = VIH VI = VCC or GND VOLD = 1.65 V max VOHD = 3.85 V min 2.9 4.4 5.4 2.56 3.86 4.86 0.002 0.001 0.001 2.1 3.15 3.85 Typ. 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 Value T A = 25 oC Max. -40 to 85 o C Min . 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.46 3.76 4.76 0.1 0.1 0.1 0.36 0.36 0.36 ±0.1 ±0.5 0.1 0.1 0.1 0.44 0.44 0.44 ±1 ±5 0.9 1.35 1.65 Max. Unit V V V V µA µA ICC IOLD IOHD 5.5 5.5 8 80 75 -75 µA mA mA 1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50 Ω. (*) All outputs loaded. 4/10 74AC373 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = t f =3 ns) Symbol Parameter V CC (V) tPLH tPHL tPLH tPHL tPZL tPZH tPLZ tPHZ tw ts th Propagation Delay Time LE to Q Propagation Delay Time D to Q Output EnableTime Output Disable Time Clock Pulse Width HIGH or LOW Setup Time Q to CK HIGH or LOW Hold Time Q to CK HIGH or LOW 3.3 5.0(**) 3.3(*) 5.0 (**) (*) T est Cond ition Value T A = 25 oC -40 to 85 o C Min. Typ. Max. Min . Max. 6.5 5.0 6.5 5.0 7.0 5.0 7.5 6.5 1.5 1.5 0.5 0.5 -0.5 -0.5 12.0 9.5 12.0 9.5 11.0 8.5 12.0 9.0 5.5 4.0 5.5 4.0 1.0 1.0 14.0 10.5 14.0 10.5 13.0 9.5 13.0 10.0 6.0 4.5 6.0 4.5 5.0 5.0 Unit ns ns ns ns ns ns ns 3.3(*) 5.0(**) 3.3 5.0(**) 3.3(*) 5.0 (**) (*) (*) 3.3 (**) 5.0 3.3 5.0 (*) (**) (*) Voltage range is 3.3V ± 0.3V (**) Voltage range is 5V ± 0.5V CAPACITIVE CHARACTERISTICS Symbol Parameter V CC (V) C OUT CIN C PD Output Capacitance Input Capacitance Power Dissipation Capacitance (note 1) 5.0 5.0 5.0 Test Con dition s Min. Typ. 8 4 20 Value T A = 25 oC Max. -40 to 85 o C Min . Max. pF pF pF Unit 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/n (per circuit) 5/10 74AC373 TEST CIRCUIT TEST t PLH, tPHL t PZL, tPLZ t PZH, tPHZ CL = 50 pF or equivalent (includes jig and probe capacitance) RL = R1 = 500Ω or equivalent RT =ZOUT of pulse generator (typically 50Ω) SWITCH Open 2VCC Open WAVEFORM 1: LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn TO LE SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) 6/10 74AC373 WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle) WAVEFORM 3: PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) 7/10 74AC373 Plastic DIP20 (0.25) MECHANICAL DATA mm MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.34 8.5 2.54 22.86 7.1 3.93 0.130 0.053 0.254 1.39 0.45 0.25 25.4 0.335 0.100 0.900 0.280 0.155 1.65 TYP. MAX. MIN. 0.010 0.055 0.018 0.010 1.000 0.065 inch TYP. MAX. DIM. P001J 8/10 74AC373 SO20 MECHANICAL DATA DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F L M S 7.40 0.50 12.60 10.00 1.27 11.43 7.60 1.27 0.75 8° (max.) 0.291 0.19 13.00 10.65 0.35 0.23 0.50 45° (typ.) 0.496 0.393 0.050 0.450 0.299 0.050 0.029 0.512 0.419 0.10 mm TYP. MAX. 2.65 0.20 2.45 0.49 0.32 0.013 0.009 0.020 0.004 MIN. inch TYP. MAX. 0.104 0.007 0.096 0.019 0.012 P013L 9/10 74AC373 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersede and replaces all information previously supplied. s SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics. © 1997 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A . 10/10