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www.DataSheet4U.com 3.3 VOLT CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 IDT72V201, IDT72V211 IDT72V221, IDT72V231 IDT72V241, IDT72V251 FEATURES: • • • • • • • • • • • • • • • • • • 256 x 9-bit organization IDT72V201 512 x 9-bit organization IDT72V211 1,024 x 9-bit organization IDT72V221 2,048 x 9-bit organization IDT72V231 4,096 x 9-bit organization IDT72V241 8,192 x 9-bit organization IDT72V251 10 ns read/write cycle time 5V input tolerant Read and Write clocks can be independent Dual-Ported zero fall-through time architecture Empty and Full Flags signal FIFO status Programmable Almost-Empty and Almost-Full flags can be set to any depth Programmable Almost-Empty and Almost-Full flags default to Empty+7, and Full-7, respectively Output Enable puts output data bus in high-impedance state Advanced submicron CMOS technology Available in 32-pin plastic leaded chip carrier (PLCC) and 32-pin plastic Thin Quad FlatPack (TQFP) Industrial temperature range (–40°C to +85°C) is available ° ° Green parts available, see ordering information DESCRIPTION: The IDT72V201/72V211/72V221/72V231/72V241/72V251 SyncFIFOs™ are very high-speed, low-power First-In, First-Out (FIFO) memories with clocked read and write controls. The architecture, functional operation and pin assignments are identical to those of the IDT72201/72211/72221/72231/ 72241/72251, but operate at a power supply voltage (Vcc) between 3.0V and 3.6V. These devices have a 256, 512, 1,024, 2,048, 4,096 and 8,192 x 9-bit memory array, respectively. These FIFOs are applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. These FIFOs have 9-bit input and output ports. The input port is controlled by a free-running clock (WCLK), and two Write Enable pins (WEN1, WEN2). Data is written into the Synchronous FIFO on every rising clock edge when the Write Enable pins are asserted. The output port is controlled by another clock pin (RCLK) and two Read Enable pins (REN1, REN2). The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation. An Output Enable pin (OE) is provided on the read port for three-state control of the output. The Synchronous FIFOs have two fixed flags, Empty (EF) and Full (FF). Two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF), are provided for improved system control. The programmable flags default to Empty+7 and Full-7 for PAE and PAF, respectively. The programmable flag offset loading is controlled by a simple state machine and is initiated by asserting the Load pin (LD). These FIFOs are fabricated using IDT's high-speed submicron CMOS technology. FUNCTIONAL BLOCK DIAGRAM WCLK WEN1 WEN2 INPUT REGISTER OFFSET REGISTER EF PAE PAF FF D0 - D8 LD WRITE CONTROL LOGIC RAM ARRAY 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 FLAG LOGIC WRITE POINTER READ POINTER READ CONTROL LOGIC OUTPUT REGISTER RESET LOGIC RCLK REN1 REN2 RS OE Q0 - Q8 4092 drw 01 IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1 ©2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2006 DSC-4092/4 IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™ www.DataSheet4U.com 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN CONFIGURATION RS D2 D3 D4 D5 D6 D7 D8 D5 D6 INDEX INDEX 32 31 30 29 28 27 26 25 D1 D0 PAF PAE GND REN1 RCLK REN2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 OE EF Q0 Q1 4092 drw02 4 24 23 22 21 20 19 18 17 WEN1 WCLK WEN2/LD VCC Q8 Q7 Q6 Q5 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 RS WEN1 WCLK WEN2/LD VCC Q8 Q7 Q6 Q5 D1 D0 PAF PAE GND REN1 RCLK REN2 OE 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 EF FF Q0 Q1 Q2 Q3 Q2 Q3 FF Q4 Q4 D8 D2 D3 D4 D7 4092 drw02a TQFP (PR32-1, order code: PF) TOP VIEW PLCC (J32-1, order code: J) TOP VIEW PIN DESCRIPTIONS Symbol D0-D8 RS WCLK WEN1 WEN2/LD Q0-Q8 RCLK REN1 REN2 OE EF PAE PAF FF VCC GND I/O Description I Data inputs for a 9-bit bus. I When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF and PAF go HIGH, and PAE and EF go LOW. A Reset is required before an initial Write after power-up. Write Clock I Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write Enable(s) are asserted. Write Enable 1 I If the FIFO is configured to have programmable flags, WEN1 is the only Write Enable pin. When WEN1 is LOW, data is written into the FIFO on every LOW-to-HIGH transition WCLK. If the FIFO is configured to have two write enables, WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is LOW. Write Enable 2/ I The FIFO is configured at Reset to have either two write enables or programmable flags. If WEN2/LD Load is HIGH at Reset, this pin operates as a second write enable. If WEN2/LD is LOW at Reset, this pin operates as a control to load and read the programmable flag offsets. If the FIFO is configured to have two write enables, WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW to write or read the programmable flag offsets. Data Outputs O Data outputs for a 9-bit bus. Read Clock I Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN1 and REN2 are asserted. Read Enable 1 I When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data will not be read from the FIFO if the EF is LOW. Read Enable 2 I When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data will not be read from the FIFO if the EF is COMMERCIAL AND INDUSTRIAL LOW. TEMPERATURE RANGES Output Enable I When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance state. Empty Flag O When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK. Programmable O When PAE is LOW, the FIFO is almost-empty based on the offset programmed into the FIFO. The default Almost-Empty Flag offset at reset is Empty+7. PAE is synchronized to RCLK. Programmable O When PAF is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default Almost-Full Flag offset at reset is Full-7. PAF is synchronized to WCLK. Full Flag O When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO is not full. FF is synchronized to WCLK. Power One 3.3V volt power supply pin. Ground One 0 volt ground pin. 2TEMPERATURE RANGES FEBRUARY 8, 2006 Name Data Inputs Reset IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™ www.DataSheet4U.com 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM(2) TSTG IOUT Rating Terminal Voltage with Respect to GND Storage Temperature DC Output Current Com'l & Ind'l –0.5 to +5 –55 to +125 –50 to +50 Unit V °C mA RECOMMENDED OPERATING CONDITIONS Symbol VCC GND VIH VIL TA TA Parameter Supply Voltage Commercial/Industrial Supply Voltage Input High Voltage Commercial/Industrial Input Low Voltage Commercial/Industrial Operating Temperature Commercial Operating Temperature Industrial Min. 3.0 0 2.0 -0.5 0 -40 Typ. 3.3 0 — — — — Max. 3.6 0 5.5 0.8 70 85 Unit V V V V °C °C NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminal only. DC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.3V, TA = -40°C to +85°C) IDT72V201 IDT72V211 IDT72V221 IDT72V231 IDT72V241 IDT72V251 Commercial and Industrial(1) tCLK = 10, 15, 20 ns Typ. — — — — — — Symbol ILI (2) Parameter Input Leakage Current (Any Input) Output Leakage Current Output Logic “1” Voltage, IOH = –2mA Output Logic “0” Voltage, IOL = 8mA Active Power Supply Current Standby Current Min. –1 –10 2.4 — — — Max. 1 10 — 0.4 20 5 Unit µA µA V V mA mA ILO(3) VOH VOL ICC1(4,5,6) ICC2 (4,7) NOTES: 1. Industrial temperature range product for the 15ns speed grade is available as a standard device. All other speed grades are available by special order. 2. Measurements with 0.4 ≤ VIN ≤ VCC. 3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC. 4. Tested with outputs disabled (IOUT = 0). 5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz. 6. Typical ICC1 = 0.17 + 0.48*fS + 0.02*CL*fS (in mA) with VCC = 3.3V, TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF). 7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz. CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol CIN(2) COUT(1,2) Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 10 10 Unit pF pF NOTES: 1. With output deselected (OE ≥ VIH). 2. Characterized values, not currently tested. 3 FEBRUARY 8, 2006 IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™ www.DataSheet4U.com 256 x 9, 512 x 9, 1,