(68HCxx05J5A) 8-bit microcontroller units

Freescale Semiconductor, Inc. HC05J5AGRS/H REV 2.1 Freescale Semiconductor, Inc... 68HC05J5A 68HRC05J5A 68HC705J5A 68HRC705J5A SPECIFICATION (General Release) www.DataSheet4U.com July 16, 1999 Semiconductor Products Sector For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. July 16, 1999 GENERAL RELEASE SPECIFICATION TABLE OF CONTENTS Section SECTION 1 GENERAL DESCRIPTION 1.1 1.2 1.3 1.4 1.5 1.5.1 1.5.2 1.5.3 1.5.4 1.5.5 1.5.6 FEATURES ...................................................................................................... 1-1 MASK OPTIONS.............................................................................................. 1-2 MCU STRUCTURE.......................................................................................... 1-2 PIN ASSIGNMENTS ........................................................................................ 1-4 FUNCTIONAL PIN DESCRIPTION.................................................................. 1-4 VDD AND VSS .............................................................................................. 1-4 OSC1, OSC2/R............................................................................................ 1-4 RESET......................................................................................................... 1-6 IRQ (MASKABLE INTERRUPT REQUEST)................................................ 1-6 PA0-PA7 ...................................................................................................... 1-6 PB0-PB5 ...................................................................................................... 1-7 SECTION 2 MEMORY 2.1 2.2 2.3 2.4 I/O AND CONTROL REGISTERS ................................................................... 2-2 RAM ................................................................................................................. 2-2 ROM................................................................................................................. 2-2 I/O REGISTERS SUMMARY ........................................................................... 2-3 SECTION 3 CENTRAL PROCESSING UNIT 3.1 3.2 3.3 3.4 3.5 3.6 3.6.1 3.6.2 3.6.3 3.6.4 3.6.5 REGISTERS .................................................................................................... 3-1 ACCUMULATOR (A)........................................................................................ 3-2 INDEX REGISTER (X) ..................................................................................... 3-2 STACK POINTER (SP) .................................................................................... 3-2 PROGRAM COUNTER (PC) ........................................................................... 3-2 CONDITION CODE REGISTER (CCR) ........................................................... 3-3 Half Carry Bit (H-Bit) .................................................................................... 3-3 Interrupt Mask (I-Bit) .................................................................................... 3-3 Negative Bit (N-Bit) ...................................................................................... 3-3 Zero Bit (Z-Bit) ............................................................................................. 3-3 Carry/Borrow Bit (C-Bit) ............................................................................... 3-4 SECTION 4 INTERRUPTS 4.1 4.2 4.3 4.4 4.5 4.5.1 CPU INTERRUPT PROCESSING ................................................................... 4-1 RESET INTERRUPT SEQUENCE .................................................................. 4-2 SOFTWARE INTERRUPT (SWI) ..................................................................... 4-3 HARDWARE INTERRUPTS ............................................................................ 4-3 EXTERNAL INTERRUPT (IRQ)....................................................................... 4-3 IRQ CONTROL/STATUS REGISTER (ICSR) $0A...................................... 4-5 i For More Information On This Product, Go to: www.freescale.com Page Freescale Semiconductor, Inc... REV 2.1 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION July 16, 1999 TABLE OF CONTENTS Section 4.5.2 4.5.3 4.5.4 Page OPTIONAL EXTERNAL INTERRUPTS (PA0-PA3) .................................... 4-6 TIMER INTERRUPT (MFT) ......................................................................... 4-7 TIMER1 INTERRUPT (16-BIT TIMER)........................................................ 4-7 SECTION 5 RESETS 5.1 EXTERNAL RESET (RESET).......................................................................... 5-2 5.2 INTERNAL RESETS ........................................................................................ 5-2 5.2.1 POWER-ON RESET (POR) ........................................................................ 5-2 5.2.2 COMPUTER OPERATING PROPERLY RESET (COPR)........................... 5-2 5.2.3 LOW VOLTAGE RESET (LVR) ................................................................... 5-3 5.2.4 ILLEGAL ADDRESS RESET (ILADR)......................................................... 5-3 SECTION 6 LOW POWER MODES 6.1 6.1.1 6.1.2 6.2 6.3 6.4 STOP INSTRUCTION...................................................................................... 6-2 STOP Mode ................................................................................................. 6-3 HALT Mode.................................................................................................. 6-3 WAIT INSTRUCTION....................................................................................... 6-4 DATA-RETENTION MODE.............................................................................. 6-4 COP WATCHDOG TIMER CONSIDERATIONS ............................................. 6-4 SECTION 7 INPUT/OUTPUT PORTS 7.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.3 7.3.1 7.3.2 7.3.3 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 SLOW OUTPUT FALLING-EDGE TRANSITION............................................. 7-1 PORT A............................................................................................................ 7-1 Port A Data Register.................................................................................... 7-2 Port A Data Direction Register..................................................................... 7-2 Port A Pulldown/up Register........................................................................ 7-3 Port A Drive Capability................................................................................. 7-3 Port A I/O Pin Interrupts............................................................................... 7-3 PORT B............................................................................................................ 7-4 Port B Data Register.................................................................................... 7-4 Port B Data Direction Register..................................................................... 7-5 Port B Pulldown/up Register........................................................................ 7-5 I/O PORT PROGRAMMING ............................................................................ 7-6 Pin Data Direction........................................................................................ 7-6 Output Pin.................................................................................................... 7-6 Input Pin....................................................................................................... 7-6 I/O Pin Transitions ....................................................................................... 7-7 I/O Pin Truth Tables..................................................................................... 7-7 Freescale Semiconductor, Inc... ii For More Information On This Product, Go to: www.freescale.com MC68HC05J5A REV 2.1 Freescale Semiconductor, Inc. July 16, 1999 GENERAL RELEASE SPECIFICATION TABLE OF CONTENTS Section SECTION 8 MULTI-FUNCTION TIMER 8.1 8.2 8.3 8.3.1 8.3.2 8.4 8.5 OVERVIEW...................................................................................................... 8-2 COMPUTER OPERATING PROPERLY (COP) WATCHDOG ........................ 8-2 MFT REGISTERS ............................................................................................ 8-2 Timer Counter Register (TCR) $09.............................................................. 8-3 Timer Control/Status Register (TCSR) $08 ................................................. 8-3 OPERATION DURING STOP MODE .............................................................. 8-5 OPERATION DURING WAIT/HALT MODE..................................................... 8-5 SECTION 9 16-BIT TIMER 9.1 9.2 9.3 9.4 9.5 9.6 9.7 TIMER1 COUNTER REGISTERS (TCNTH, TCNTL) ...................................... 9-2 ALTERNATE COUNTER REGISTERS (ACNTH, ACNTL).............................. 9-3 INPUT CAPTURE REGISTERS ...................................................................... 9-5 TIMER1 CONTROL REGISTER (T1CR) ......................................................... 9-8 TIMER1 STATUS REGISTER (T1SR)............................................................. 9-9 TIMER1 OPERATION DURING WAIT MODE................................................. 9-9 TIMER1 OPERATION DURING STOP MODE ................................................ 9-9 SECTION 10 INSTRUCTION SET 10.1 ADDRESSING MODES ................................................................................. 10-1 10.1.1 Inherent...................................................................................................... 10-1 10.1.2 Immediate .................................................................................................. 10-1 10.1.3 Direct ........................