High-Speed CMOS Logic Dual Retriggerable Precision Monostable Multivibrator

CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538 Data sheet acquired from Harris Semiconductor SCHS123E June 1998 - Revised October 2003 High-Speed CMOS Logic Dual Retriggerable Precision Monostable Multivibrator Description The ’HC4538 and ’HCT4538 are dual retriggerable/resettable monostable precision multivibrators for fixed voltage timing applications. An external resistor (RX) and an external capacitor (CX) control the timing and the accuracy for the circuit. Adjustment of RX and CX provides a wide range of output pulse widths from the Q and Q terminals. The propagation delay from trigger input-tooutput transition and the propagation delay from reset inputto-output transition are independent of RX and CX. Leading-edge triggering (A) and trailing edge triggering (B) inputs are provided for triggering from either edge of the input pulse. An unused “A” input should be tied to GND and an unused B should be tied to VCC. On power up the IC is reset. Unused resets and sections must be terminated. In normal operation the circuit retriggers on the application of each new trigger pulse. To operate in the non-triggerable mode Q is connected to B when leading edge triggering (A) is used or Q is connected to A when trailing edge triggering (B) is used. The period (τ) can be calculated from τ = (0.7) RX, CX; RMIN is 5kΩ. CMIN is 0pF. Features • Retriggerable/Resettable Capability • Trigger and Reset Propagation Delays Independent of RX, CX • Triggering from the Leading or Trailing Edge • Q and Q Buffered Outputs Available • Separate Resets • Wide Range of Output Pulse Widths • Schmitt Trigger Input on A and B Inputs • Retrigger Time is Independent of CX • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times [ /Title (CD54 HC453 8, CD74 HC453 8, CD74 HCT45 38) /Subject (High Speed CMOS Logic • Significant Power Reduction Compared to LSTTL Logic ICs www.DataSheet4U.com Ordering • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Information TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld SOP 16 Ld TSSOP 16 Ld TSSOP 16 Ld TSSOP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC PART NUMBER CD54HC4538F3A CD54HCT4538F3A CD74HC4538E CD74HC4538M CD74HC4538MT CD74HC4538M96 Pinout CD54HC4538, CD54HCT4538 (CERDIP) CD74HC4538 (PDIP, SOIC, SOP, TSSOP) CD74HCT4538 (PDIP, SOIC) TOP VIEW 1CX 1 1RXCX 2 1R 3 1A 4 1B 5 1Q 6 1Q 7 GND 8 16 VCC 15 2CX 14 2RXCX 13 2R 12 2A 11 2B 10 2Q 9 2Q CD74HC4538NSR CD74HC4538PW CD74HC4538PWR CD74HC4538PWT CD74HCT4538E CD74HCT4538M CD74HCT4538MT CD74HCT4538M96 NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1 CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538 Functional Diagram 1Cx 1 1Cx 4 1A 5 1B 3 1R 13 12 2A 11 2B 2Cx 15 GND = 8 VCC = 16 2Cx 2RxCx 14 VCC 2Rx MONO 2 9 2Q 10 2Q MONO 1 7 1Q 2 1RxCx 6 1Q 1Rx VCC 2R TRUTH TABLE R2 INPUTS R L X X H H A X H X L ↑ B X X L ↓ H Q L L L OUTPUTS Q H D CL R1 CL p n CL CL Q p n CL CL p n CL Q H H R1 H = High Level, L = Low Level, ↑ = Transition from Low to High, ↓ = Transition from High to Low, One High Level Pulse, One Low Level Pulse, X = Irrelevant. FIGURE 1. FF DETAIL 2 CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538 16 VCC VCC VCC VCC RX 2(14) CX 1(15) R2 VCC R1 + COMP II 6(10) Q - 8 VCC HIGH Z 7(9) Q 3(13) R VCC 4(12) A 5(11) B D R1 CL FF CL R2 Q Q FIGURE 2. LOGIC DIAGRAM (1 MONO) FUNCTIONAL TERMINAL CONNECTIONS VCC TO TERMINAL NUMBER FUNCTION Leading-Edge Trigger/Retriggerable Leading-Edge Trigger/Non-Retriggerable Trailing-Edge Trigger/Retriggerable Trailing-Edge Trigger/Non-Retriggerable NOTES: 1. A retriggerable one-shot multivibrator has an output pulse width which is extended one full time period (T) after application of the last trigger pulse. 2. A non-triggerable one-shot multivibrator has a time period (T) referenced from the application of the first trigger pulse. MONO1 3, 5 3 3 3 MONO2 11, 13 13 13 13 4 12 GND TO TERMINAL NUMBER MONO1 MONO2 INPUT PULSE TO TERMINAL NUMBER MONO1 4 4 5 5 MONO2 12 12 11 11 4-6 12-10 5-7 11-9 OTHER CONNECTIONS MONO1 MONO2 T T FIGURE 3. INPUT PULSE TRAIN FIGURE 4. RETRIGGERABLE MODE PULSE WIDTH (A MODE) FIGURE 5. NON-RETRIGGERABLE MODE PULSE WIDTH (A MODE) 3 CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538 Absolute Maximum Ratings DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Thermal Information Package Thermal Impedance, θJA (see Note 5): E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC (Note 3) HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Times, tr, tf Reset Input: 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) Trigger Inputs A or B: 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited (Max) External Timing Resistor, RX (Note 4) . . . . . . . . . . . . . . . .5kΩ (Min) External Timing Capacitor, CX (Note 4) . . . . . . . . . . . . . . . . . 0 (Min) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 3. Unless otherwise specified, all voltages are referenced to ground. 4. The maximum allowable values of RX and CX are a function of leakage of capacitor CX, the leakage of the ’HC4538, and leakage due to board layout and surface resistance. Values of RX and CX should be chosen so that the maximum current into pin 2 or pin 14 is 30mA. Susceptibility to externally induced noise signals may occur for RX > 1MΩ. 5. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 2 4.5 6 4.5 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 V V V V V V V V V V V V SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS 4 CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538 DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current A, B, R Input Leakage Current RXCX (Note 6) Quiescent Device Current Active Device Current Q = High & Pins 2, 14 at VCC/4 HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Input Leakage Current RXCX (Note 6) Quiescent Device Current Active Device Current Q = High & Pins 2, 14 at VCC/4 Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTES: 6. When testing IIL the Q output must be high. If Q is low (device not triggered) the pull-up P device will be ON and the low resistance path from VDD to the test pin will cause a current far exceeding the specification. 7. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. ICC ICC VCC or GND VCC or GND VCC -2.1 II VCC and GND VOL VIH or VIL VIH VIL VOH VIH or VIL -0.0