16-bit Digital Signal Controllers

56F826 Data Sheet Preliminary Technical Data www.DataSheet4U.com 56F800 16-bit Digital Signal Controllers DSP56F826 Rev. 14 01/2007 freescale.com 56F826 General Description • • • • Up to 40 MIPS at 80MHz core frequency DSP and MCU functionality in a unified, C-efficient architecture Hardware DO and REP loops MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes 31.5K × 16-bit words (64KB) Program Flash 512 × 16-bit words (1KB) Program RAM 2K × 16-bit words (4KB) Data Flash 4K × 16-bit words (8KB) Data RAM 2K × 16-bit words (4KB) BootFLASH Up to 64K × 16-bit words each of external memory expansion for Program and Data memory • • • • • • • • One Serial Port Interface (SPI) One additional SPI or two optional Serial Communication Interfaces (SCI) One Synchronous Serial Interface (SSI) One General Purpose Quad Timer JTAG/OnCE™ for debugging 100-pin LQFP Package 16 dedicated and 30 shared GPIO Time-of-Day (TOD) Timer • • • • • • EXTBOOT RESET IRQA IRQB 6 JTAG/ OnCE Port TOD Timer Interrupt Controller Program Controller and Hardware Looping Unit Address Generation Unit Data ALU 16 x 16 + 36 → 36-Bit MAC Three 16-bit Input Registers Two 36-bit Accumulators Bit Manipulation Unit VDD 3 VSS 4 4 VDDIO VSSIO 4 Analog Reg VDDA VSSA Low Voltage Supervisor 4 Quad Timer or GPIO Program Memory 32252 x 16 Flash 512 x 16 SRAM Boot Flash 2048 x 16 Flash Data Memory 2048 x 16 Flash 4096 x 16 SRAM PAB PDB XDB2 CGDB XAB1 XAB2 INTERRUPT CONTROLS 16 IPBB CONTROLS 16 16-Bit 56800 Core PLL Clock Gen CLKO XTAL EXTAL 6 SSI or GPIO SCI0 & SCI1 or SPI0 SPI1 or GPIO Dedicated GPIO 4 COP/ Watchdog COP RESET MODULE CONTROLS ADDRESS BUS [8:0] DATA BUS [15:0] External Address Bus Switch 16 A[00:15] or GPIO D[00:15] 4 16 Application-Specific Memory & Peripherals IPBus Bridge (IPBB) External Bus Interface Unit External Data Bus Switch Bus Control 16 PS Select[0] DS Select[1] WR Enable RD Enable 56F826 Block Diagram 56F826 Technical Data, Rev. 14 Freescale Semiconductor 3 Part 1 Overview 1.1 56F826 Features 1.1.1 • • • • • • • • • • • • • • Processing Core Efficient 16-bit 56800 family controller engine with dual Harvard architecture As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) Two 36-bit accumulators, including extension bits 16-bit bidirectional barrel shifter Parallel instruction set with unique processor addressing modes Hardware DO and REP loops Three internal address buses and one external address bus Four internal data buses and one external data bus Instruction set supports both DSP and controller functions Controller-style addressing modes and instructions for compact code Efficient C Compiler and local variable support Software subroutine and interrupt stack with depth limited only by memory JTAG/OnCE Debug Programming Interface 1.1.2 • • Memory Harvard architecture permits as many as three simultaneous accesses to Program and Data memory On-chip memory including a low-cost, high-volume Flash solution — 31.5K × 16-bit words of Program Flash — 512 × 16-bit words of Program RAM — 2K × 16-bit words of Data Flash — 4K × 16-bit words of Data RAM — 2K × 16-bit words of BootFLASH • Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states — As much as 64K × 16-bit Data memory — As much as 64K × 16-bit Program memory 1.1.3 • • • • Peripheral Circuits for 56F826 One General Purpose Quad Timer totalling 7 pins One Serial Peripheral Interface with 4 pins (or four additional GPIO lines) One Serial Peripheral Interface, or multiplexed with two Serial Communications Interfaces totalling 4 pins Synchronous Serial Interface (SSI) with configurable six-pin port (or six additional GPIO lines) 56F826 Technical Data, Rev. 14 4 Freescale Semiconductor 56F826 Description • • • • • • • • • Sixteen (16) dedicated General Purpose I/O (GPIO) pins Thirty (30) shared General Purpose I/O (GPIO) pins Computer-Operating Properly (COP) Watchdog timer Two external interrupt pins External reset pin for hardware reset JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock Fabricated in high-density EMOS with 5V-tolerant, TTL-compatible digital inputs One Time of Day module 1.1.4 • • Energy Information Dual power supply, 3.3V and 2.5V Wait and Multiple Stop modes available 1.2 56F826 Description The 56F826 is a member of the 56800 core-based family of processors. It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution for general purpose applications. Because of its low cost, configuration flexibility, and compact program code, the 56F826 is well-suited for many applications. The 56F826 includes many peripherals that are especially useful for applications such as: noise suppression, ID tag readers, sonic/subsonic detectors, security access devices, remote metering, sonic alarms, POS terminals, feature phones. The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both DSP and MCU applications. The instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized control applications. The 56F826 supports program execution from either internal or external memories. Two data operands can be accessed from the on-chip Data RAM per instruction cycle. The 56F826 also provides two external dedicated interrupt lines, and up to 46 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. The 56F826 controller includes 31.5K words (16-bit) of Program Flash and 2K words of Data Flash (each programmable through the JTAG port) with 512 words of Program RAM, and 4K words of Data RAM. It also supports program execution from external memory. The 56F826 incorporates a total of 2K words of Boot Flash for easy customer-inclusion of field-programmable software routines that can be used to program the main Program and Data Flash memory areas. Both Program and Data Flash memories can be independently bulk-erased or erased in page sizes of 256 words. The Boot Flash memory can also be either bulk- or page-erased. 56F826 Technical Data, Rev. 14 Freescale Semiconductor 5 This controller also provides a full set of standard programmable peripherals including one Synchronous Serial Interface (SSI), one Serial Peripheral Interface (SPI), the option to select a second SPI or two Serial Communications Interfaces (SCIs), and one Quad Timer. The SSI, SPI, and Quad Timer can be used as General Purpose Input/Outputs (GPIOs) if a timer function is not required. 1.3 Award-Winning Development Environment • • Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system. The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development. 1.4 Product Documentation The four documents listed in Table 1-1 are required for a complete description and proper design with the 56F826. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, or online at www.freescale.com. Table 1-1 56F826 Chip Documentation Topic 56800E Family Manual DSP56F826/F827 User’s Manual 56F826 Technical Data Sheet 56F826 Product Brief 56F826 Errata Description Detailed description of the 56800 family architecture, and 16-bit core processor and the instruction set Detailed description of memory, peripherals, and interfaces of the 56F826 and 56F827 Electrical and timing specifications, pin descriptions, and package descriptions (this document) Summary description and block diagram of the 56F826 core, memory, peripherals and interfaces Details any chip issues that might be present Order Number 56800EFM DSP56F826-827UM DSP56F826 DSP56F826PB DSP56F826E 56F826 Technical Data, Rev. 14 6 Freescale Semiconductor Data Sheet Conventions 1.5 Data Sheet Conventions This data sheet uses the following conventions: OVERBAR “asserted” “deasserted” Examples: This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low. A high true (active high) signal is high or a low true (active low) signal is low. A high true (active high) signal is low or a low true (active low) signal is high. Signal/Symbol PIN PIN PIN PIN Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage1 VIL/VOL VIH/VOH VIH/VOH VIL/VOL 1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. 56F826 Technical Data, Rev. 14 Freescale Semiconductor 7 Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F826 are organized into functional groups, as shown in Table 2-1 and as illustrated in Figure 2-1. Table 2-1 describes the signal or signals present on a pin. Table 2-1 Functional Group Pin Allocations Functional Group Power (VDD, VDDIO or VDDA) Ground (VSS, VSSIO or VSSA) PLL and Clock Address Bus1 Data Bus1 Bus Control Qu