(56F8166 / 56F8366) 16-bit Digital Signal Controllers

www.DataSheet4U.com 56F8366/56F8166 Data Sheet Preliminary Technical Data 56F8300 16-bit Digital Signal Controllers MC56F8366 Rev. 6 01/2007 freescale.com Document Revision History Version History Rev 0 Rev 1.0 Rev 2.0 Pre-release, Alpha customers only Initial Public Release Added output voltage maximum value and note to clarify in Table 10-1; also removed overall life expectancy note, since life expectancy is dependent on customer usage and must be determined by reliability engineering. Clarified value and unit measure for Maximum allowed PD in Table 10-3. Corrected note about average value for Flash Data Retention in Table 10-4. Added new RoHS-compliant orderable part numbers in Table 13-1. Deleted formula for Max Ambient Operating Temperature (Automotive) and Max Ambient Operating Temperature (Industrial) and corrected Flash Endurance to 10,000 in Table 10-4. Added RoHS-compliance and “pb-free” language to back cover Added information/corrected state during reset in Table 2-2. Clarified external reference crystal frequency for PLL in Table 10-14 by increasing maximum value to 8.4MHz. Replaced “Tri-stated” with an explanation in State During Reset column in Table 2-2. • Added the following note to the description of the TMS signal in Table 2-2: Note: Always tie the TMS pin to VDD through a 2.2K resistor. • Added the following note to the description of the TRST signal in Table 2-2: Note: For normal operation, connect TRST directly to VSS. If the design is to be used in a debugging environment, TRST may be tied to VSS through a 1K resistor. Description of Change Rev 3.0 Rev 4.0 Rev 5.0 Rev. 6 Please see http://www.freescale.com for the most current data sheet revision. 56F8366 Technical Data, Rev. 6 2 Freescale Semiconductor Preliminary 56F8366/56F8166 General Description Note: Features in italics are NOT available in the 56F8166 device. • Up to 60 MIPS at 60MHz core frequency • DSP and MCU functionality in a unified, C-efficient architecture • Access up to 1MB of off-chip program and data memory • Chip Select Logic for glueless interface to ROM and SRAM • 512KB of Program Flash • 4KB of Program RAM • 32KB of Data Flash • 32KB of Data RAM • 32KB of Boot Flash • Up to two 6-channel PWM modules • Four 4-channel, 12-bit ADCs • • • • • • • • • Temperature Sensor Up to two Quadrature Decoders Optional On-Chip Regulator Up to two FlexCAN modules Two Serial Communication Interfaces (SCIs) Up to two Serial Peripheral Interfaces (SPIs) Up to four General Purpose Quad Timers Computer Operating Properly (COP) / Watchdog JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging • Up to 62 GPIO lines • 144-pin LQFP Package RSTO EMI_MODE EXTBOOT 5 VPP 2 VCAP 4 OCR_DIS VDD VSS 7 5 Digital Reg VDDA 2 VSSA RESET 6 3 3 6 3 4 4 4 5 4 4 PWM Outputs Current Sense Inputs or GPIOC Fault Inputs PWM Outputs Current Sense Inputs or GPIOD Fault Inputs AD0 AD1 VREF AD0 AD1 PWMA JTAG/ EOnCE Port Analog Reg 16-Bit 56800E Core Low Voltage Supervisor Bit Manipulation Unit PWMB Program Controller and Hardware Looping Unit Address Generation Unit Data ALU 16 x 16 + 36 -> 36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators ADCA PAB PDB CDBR CDBW Memory ADCB Program Memory 256K x 16 Flash 2K x 16 RAM Boot ROM 16K x 16 Flash R/W Control XDB2 XAB1 XAB2 6 External Address Bus Switch 2 8 7 9 A0-5 or GPIOA8-13 A6-7 or GPIOE2-3 A8-15 or GPIOA0-7 GPIOB0 or A16 D0-6 or GPIOF9-15 D7-15 or GPIOF0-8 WR RD PS / CS0 (GPIOD8) DS / CS1 (GPIOD9) GPIOD0 (CS2 or CAN2_TX) GPIOD1 (CS3 or CAN2_RX) Temp_Sense Quadrature Decoder 0 or Quad Timer A or GPIOC Quadrature Decoder 1 or Quad Timer B or SPI1 or GPIOC Quad Timer C or GPIOE Quad Timer D or GPIOE FlexCAN 4 Data Memory 16K x 16 Flash 16K x 16 RAM PDB CDBR CDBW External Bus Interface Unit P PAB System Bus Control External Data Bus Switch Bus Control 4 IPBus Bridge (IPBB) Decoding Peripherals Clock resets PLL Peripheral Device Selects RW Control IPAB IPWDB IPRDB GPIO or EMI CS or FlexCAN2 2 2 SPI0 or GPIOE 4 SCI1 or GPIOD 2 SCI0 or GPIOE 2 COP/ Watchdog Interrupt Controller IRQA IRQB System O Integration R Module CLKO O Clock Generator S C XTAL EXTAL CLKMODE 56F8366/56F8166 Block Diagram - 144 LQFP 56F8366 Technical Data, Rev. 6 Freescale Semiconductor Preliminary 3 Table of Contents Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 5 1.1. 1.2. 1.3. 1.4. 1.5. 1.6. 56F8366/56F8166 Features . . . . . . . . . . . . . 5 Device Description . . . . . . . . . . . . . . . . . . . . 7 Award-Winning Development Environment. . 9 Architecture Block Diagram . . . . . . . . . . . . 10 Product Documentation . . . . . . . . . . . . . . . 14 Data Sheet Conventions . . . . . . . . . . . . . . . 14 Part 8: General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . 137 8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . 137 8.2. Memory Maps . . . . . . . . . . . . . . . . . . . . . . 137 8.3. Configuration . . . . . . . . . . . . . . . . . . . . . . . 137 Part 9: Joint Test Action Group (JTAG) . . 142 9.1. JTAG Information . . . . . . . . . . . . . . . . . . . . 142 Part 2: Signal/Connection Descriptions . . 15 2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . 18 Part 10: Specifications . . . . . . . . . . . . . . . 143 10.1. General Characteristics . . . . . . . . . . . . . . 143 10.2. DC Electrical Characteristics. . . . . . . . . . 147 10.3. AC Electrical Characteristics . . . . . . . . . . 151 10.4. Flash Memory Characteristics. . . . . . . . . 151 10.5. External Clock Operation Timing . . . . . . . 152 10.6. Phase Locked Loop Timing . . . . . . . . . . . 152 10.7. Crystal Oscillator Timing . . . . . . . . . . . . . 153 10.8. External Memory Interface Timing . . . . . . 153 10.9. Reset, Stop, Wait, Mode Select, and Interrupt Timing . . . . . . . . . . . . . 156 10.10. Serial Peripheral Interface (SPI) Timing . . . . . . . . . . . . . . . . . 158 10.11. Quad Timer Timing . . . . . . . . . . . . . . . . 161 10.12. Quadrature Decoder Timing . . . . . . . . . 162 10.13. Serial Communication Interface (SCI) Timing . . . . . . . . . . . . . . . . 163 10.14. Controller Area Network (CAN) Timing . 163 10.15. JTAG Timing . . . . . . . . . . . . . . . . . . . . . 164 10.16. Analog-to-Digital Converter (ADC) Parameters . . . . . . . . . . . 165 10.17. Equivalent Circuit for ADC Inputs . . . . . 168 10.18. Power Consumption . . . . . . . . . . . . . . . 168 Part 3: On-Chip Clock Synthesis (OCCS) . 38 3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.2. External Clock Operation . . . . . . . . . . . . . . 38 3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Part 4: Memory Map. . . . . . . . . . . . . . . . . . . 40 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.7. 4.8. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . Program Map. . . . . . . . . . . . . . . . . . . . . . . . Interrupt Vector Table . . . . . . . . . . . . . . . . . Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Map . . . . . . . . . . . . . . . . . . . EOnCE Memory Map . . . . . . . . . . . . . . . . . Peripheral Memory Mapped Registers . . . . Factory Programmed Memor. . . . . . . . . . . . 40 41 44 47 47 49 50 82 Part 5: Interrupt Controller (ITCN) . . . . . . . . 83 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. 5.7. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 83 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Functional Description . . . . . . . . . . . . . . . . . 83 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 85 Operating Modes . . . . . . . . . . . . . . . . . . . . . 85 Register Descriptions . . . . . . . . . . . . . . . . . 86 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Part 11: Packaging . . . . . . . . . . . . . . . . . . . 170 11.1. 56F8366 Package and Pin-Out Information . . . . . . . . . . . . . . . . . . 170 11.2. 56F8166 Package and Pin-Out Information . . . . . . . . . . . . . . . . . 173 Part 6: System Integration Module (SIM) . 114 6.1. 6.2. 6.3. 6.4. 6.5. 6.6. 6.7. 6.8. 6.9. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Modes . . . . . . . . . . . . . . . . . . . Operating Mode Register . . . . . . . . . . . . . Register Descriptions . . . . . . . . . . . . . . . . Clock Generation Overview . . . . . . . . . . . Power-Down Modes Overview . . . . . . . . . Stop and Wait Mode Disable Function . . . Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 115 115 116 117 132 132 133 133 Part 12: Design Considerations . . . . . . . . 177 12.1. Thermal Design Considerations . . . . . . . . 177 12.2. Electrical Design Considerations . . . . . . . 178 12.3. Power Distribution and I/O Ring Implementation . . . . . . . . . . . . . . 179 Part 13: Ordering Information . . . . . . . . . 180 Part 7: Security Features . . . . . . . . . . . . . . 134 7.1. Operation with Security Enabled . . . . . . . 134 7.2. Flash Access Blocking Mechanisms . . . . . 134 56F8366 Technical Data, Rev. 6 4 Freescale Semiconductor Preliminary 56F8366/56F8166 Features Part 1 Overview 1.1 56F8366/56F8166 Features 1.1.1 • • • • • • • • • • • • • • Core Efficient 16-bit 56800E family controller engine with dual Harvard architecture Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) Four 36-bit accumulators, including extension bits Arithmetic and logic multi-bit shifter Parallel instruction set with unique DSP addressing modes Hardware DO and REP loops Three internal address buses Four internal data buses Instruction set supports both DSP and controller functions Co