(56F8156 / 56F8356) 16-bit Digital Signal Controllers

www.DataSheet4U.com 56F8356/56F8156 Data Sheet Preliminary Technical Data 56F8300 16-bit Digital Signal Controllers MC56F8356 Rev. 13 01/2007 freescale.com Document Revision History Version History Rev 1.0 Rev 2.0 Initial Public Release Added Package Pins to GPIO Table in Part 8 General Purpose Input/Output (GPIO). Added “Typical Min” values to Table 10-18. Editing grammar, spelling, consistency of language throughout family. Updated values in Regulator Parameters Table 10-9, External Clock Operation Timing Requirements Table 10-13, SPI Timing Table 10-18, ADC Parameters Table 10-24, and IO Loading Coefficients at 10MHz Table 10-25. Added Part 4.8, added the word “access” to FM Error Interrupt in Table 4-5, documenting only Typ. numbers for LVI in Table 10-6, updated EMI numbers and writeup in Part 10.8. Updated numbers in Table 10-7 and Table 10-8 with more recent data, Corrected typo in Table 10-3 in Pd characteristics. Replace any reference to Flash Interface Unit with Flash Memory Module; corrected thermal numbers for 144 LQFP in Table 10-3; removed unneccessary notes in Table 10-12; corrected temperature range in Table 10-14; added ADC calibration information to Table 10-24 and new graphs in Figure 10-22 Adding/clarifing notes to Table 4-4 to help clarify independent program flash blocks and other Program Flash modes, clarification to Table 10-23, corrected Digital Input Current Low (pull-up enabled) numbers in Table 10-5. Removed text and Table 10-2; replaced with note to Table 10-1. Added 56F8156 information; edited to indicate differences in 56F8356 and 56F8156. Reformatted for Freescale look and feel. Updated Temperature Sensor and ADC tables, then updated balance of electrical tables for consistency throughout family. Clarified I/O power description in Table 2-2, added note to Table 10-7 and clarified Section 12.3. Added output voltage maximum value and note to clarify in Table 10-1; also removed overall life expectancy note, since life expectancy is dependent on customer usage and must be determined by reliability engineering. Clarified value and unit measure for Maximum allowed PD in Table 10-3. Corrected note about average value for Flash Data Retention in Table 10-4. Added new RoHS-compliant orderable part numbers in Table 13-1. Updated Table 10-24 to reflect new value for maximum Uncalibrated Gain Error Deleted RSTO from Pin Group 2 (listed after Table 10-1). Deleted formula for Max Ambient Operating Temperature (Automotive) and Max Ambient Operating Temperature (Industrial) in Table 10-4. Added RoHS-compliance and “pb-free” language to back cover. Added information/corrected state during reset in Table 2-2. Clarified external reference crystal frequency for PLL in Table 10-14 by increasing maximum value to 8.4MHz.. Replaced “Tri-stated” with an explanation in State During Reset column in Table 2-2. • Added the following note to the description of the TMS signal in Table 2-2: Note: Always tie the TMS pin to VDD through a 2.2K resistor. • Added the following note to the description of the TRST signal in Table 2-2: Note: For normal operation, connect TRST directly to VSS. If the design is to be used in a debugging environment, TRST may be tied to VSS through a 1K resistor. Description of Change Rev 3.0 Rev 4.0 Rev 5.0 Rev 6.0 Rev 7.0 Rev 8.0 Rev 9.0 Rev 10.0 Rev 11.0 Rev 12.0 Rev. 13 Please see http://www.freescale.com for the most current data sheet revision. 56F8356 Technical Data, Rev. 13 2 Freescale Semiconductor Preliminary 56F8356/56F8156 General Description Note: Features in italics are NOT available in the 56F8156 device. • Up to 60 MIPS at 60MHz core frequency • DSP and MCU functionality in a unified, C-efficient architecture • Access up to 1MB of off-chip program and data memory • Chip Select Logic for glueless interface to ROM and SRAM • 256KB of Program Flash • 4KB of Program RAM • 8KB of Data Flash • 16KB of Data RAM • 16KB of Boot Flash • Up to two 6-channel PWM modules • Four 4-channel, 12-bit ADCs OCR_DIS VDD Vss 7 5 • Temperature Sensor • Up to two Quadrature Decoders • Optional on-chip regulator • FlexCAN module • Two Serial Communication Interfaces (SCIs) • Up to two Serial Peripheral Interfaces (SPIs) • Up to four general-purpose Quad Timers • Computer Operating Properly (COP) / Watchdog • JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging • Up to 62 GPIO lines • 144-pin LQFP Package RSTO 6 3 3 6 3 4 4 4 5 4 4 EMI_MODE EXTBOOT 5 VPP 2 VCAP 4 VDDA 2 VSSA RESET PWM Outputs Current Sense Inputs or GPIOC Fault Inputs PWM Outputs Current Sense Inputs or GPIOD Fault Inputs AD0 AD1 VREF AD0 PWMA JTAG/ EOnCE Port Digital Reg Analog Reg 16-Bit 56800E Core Low Voltage Supervisor Bit Manipulation Unit PWMB Program Controller and Hardware Looping Unit Address Generation Unit Data ALU 16 x 16 + 36 -> 36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators ADCA PAB PDB CDBR CDBW R/W Control XDB2 XAB1 XAB2 PAB 6 External Address Bus Switch 2 8 Memory ADCB Program Memory 128K x 16 Flash 2K x 16 RAM 8K x 16 Boot Flash A0-5 or GPIOA8-13 A6-7 or GPIOE2-3 A8-15 or GPIOA0-7 GPIOB0 or A16 AD1 TEMP_SENSE Quadrature Decoder 0 or Quad Timer A or GPIOC Quadrature Decoder 1 or Quad Timer B or SPI1 or GPIOC Quad Timer C or GPIOE Quad Timer D or GPIOE FlexCAN External Bus Interface Unit 4 Data Memory 4K x 16 Flash 8K x 16 RAM PDB CDBR CDBW System Bus Control External Data Bus Switch 7 9 D0-6 or GPIOF9-15 D7-15 or GPIOF0-8 WR RD 4 IPBus Bridge (IPBB) Decoding Peripherals Clock resets Bus Control 2 GPIOD0-1 or CS2-3 PS or CS0 or GPIOD8 DS or CS1 or GPIOD9 Peripheral Device Selects RW Control IPAB IPWDB IPRDB 1 2 2 PLL SPI0 or GPIOE 4 SCI1 or GPIOD 2 SCI0 or GPIOE 2 COP/ Watchdog Interrupt Controller P System O Integration R Module O Clock S Generator C XTAL EXTAL IRQA IRQB CLKO CLKMODE 56F8356 / 56F8156 Block Diagram 56F8356 Technical Data, Rev. 13 Freescale Semiconductor Preliminary 3 Table of Contents Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 5 1.1. 1.2. 1.3. 1.4. 1.5. 1.6. 56F8356/56F8156 Features . . . . . . . . . . . . . 5 Device Description . . . . . . . . . . . . . . . . . . . . 7 Award-Winning Development Environment. . 9 Architecture Block Diagram . . . . . . . . . . . . . 10 Product Documentation . . . . . . . . . . . . . . . . 14 Data Sheet Conventions . . . . . . . . . . . . . . . 14 Part 8: General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . 130 8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . 130 8.2. Memory Maps . . . . . . . . . . . . . . . . . . . . . . 130 8.3. Configuration. . . . . . . . . . . . . . . . . . . . . . . 130 Part 9: Joint Test Action Group (JTAG) . 136 9.1. 56F8356 Information. . . . . . . . . . . . . . . . . 136 Part 2: Signal/Connection Descriptions . . 15 2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . 18 Part 10: Specifications. . . . . . . . . . . . . . . . 136 10.1. General Characteristics . . . . . . . . . . . . . . 136 10.2. DC Electrical Characteristics. . . . . . . . . . 140 10.3. AC Electrical Characteristics . . . . . . . . . . 145 10.4. Flash Memory Characteristics. . . . . . . . . 145 10.5. External Clock Operation Timing . . . . . . . 146 10.6. Phase Locked Loop Timing. . . . . . . . . . . 146 10.7. Crystal Oscillator Timing . . . . . . . . . . . . . 147 10.8. External Memory Interface Timing . . . . . 147 10.9. Reset, Stop, Wait, Mode Select, and Interrupt Timing . . . . . . . . . . . . . . 150 10.10. Serial Peripheral Interface (SPI) Timing 153 10.11. Quad Timer Timing . . . . . . . . . . . . . . . . 157 10.12. Quadrature Decoder Timing . . . . . . . . . 158 10.13. Serial Communication Interface (SCI) Timing . . . . . . . . . . . . . . . . 159 10.14. Controller Area Network (CAN) Timing . 159 10.15. JTAG Timing . . . . . . . . . . . . . . . . . . . . . 160 10.16. Analog-to-Digital Converter (ADC) Parameters . . . . . . . . . . . 161 10.17. Equivalent Circuit for ADC Inputs . . . . . . 164 10.18. Power Consumption . . . . . . . . . . . . . . . 165 Part 3: On-Chip Clock Synthesis (OCCS) . 38 3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.2. External Clock Operation . . . . . . . . . . . . . . 38 3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Part 4: Memory Map . . . . . . . . . . . . . . . . . . . 40 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.7. 4.8. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . Program Map. . . . . . . . . . . . . . . . . . . . . . . . Interrupt Vector Table . . . . . . . . . . . . . . . . . Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Map . . . . . . . . . . . . . . . . . . . EOnCE Memory Map . . . . . . . . . . . . . . . . . Peripheral Memory Mapped Registers . . . . Factory Programmed Memory. . . . . . . . . . . 40 42 43 47 47 49 50 77 Part 5: Interrupt Controller (ITCN) . . . . . . . . 77 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. 5.7. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 77 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Functional Description . . . . . . . . . . . . . . . . . 78 Block Diagram . . . . . . . . . . . . . . . . . . . . . . 80 Operating Modes . . . . . . . . . . . . . . . . . . . . 80 Register Descriptions . . . . . . . . . . . . . . . . . 80 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Part 11: Packaging . . . . . . . . . . . . . . . . . . 167 11.1. 56F8356 Package and Pin-Out Information . . . . . . . . . . . . . . . . . 167 11.2. 56F8156 Package and Pin-Out Information . . . . . . . . . . . . . . . . . 169 Part 6: System Integration Module (SIM) . 109 6.1. 6.2. 6.3. 6.4. 6.5. 6.6. 6.7. 6.8. 6.9. Overview . . . . . . . . . . . . . . . . . . . . . . . . .