(56F8145 / 56F8345) 16-bit Digital Signal Controllers

www.DataSheet4U.com 56F8345/56F8145 Data Sheet Preliminary Technical Data 56F8300 16-bit Digital Signal Controllers MC56F8345 Rev. 17 01/2007 freescale.com Document Revision History Version History Rev 1.0 Rev 2.0 Rev 3.0 Description of Change Pre-Release version, Alpha customers only Initial Public Release Corrected typo in Table 10-4, Flash Endurance is 10,000 cycles. Addressed additional grammar issues. Added “Typical Min” values to Table 10-16. Edited grammar, spelling, consistency of language throughout family. Updated values in Current Consumption per Power Supply Pin, Table 10-7, Regulator Parameters, Table 10-9, External Clock Operation Timing Requirements Table 10-13, SPI Timing, Table 10-17, ADC Parameters, Table 10-23, and IO Loading Coefficients at 10MHz, Table 10-24. Added Part 4.8. Added the word “access” to FM Error Interrupt in Table 4-5. Removed min and max numbers. Clarified CSBAR 0 and CSBAR 1 reset values in Table 4-10. Removed min and max numbers, only documenting Typ. numbers for LVI in Table 10-6. Updated numbers in Table 10-7 and Table 10-8 with more recent data. Corrected typo in Table 10-3 in Pd characteristics. Replaced any reference to Flash Interface Unit with Flash Memory Module. Added note to VCAP pin in Table 2-3. Removed unneccessary notes in Table 10-12. Corrected temperature range in Table 10-14. Added ADC calibration information to Table 10-23 and new graphs in Figure 10-21. Clarified Table 10-22. Corrected Digital Input Current Low (pull-up enabled) numbers in Table 10-5. Removed text and Table 10-2. Replaced with note to Table 10-1. Added 56F8145 information; edited to indicate differences in 56F8345 and 56F8145. Reformatted for Freescale look and feel. Updated Temperature Sensor and ADC tables; updated balance of electrical tables for consistency throughout family. Clarified I/O power description in Table 2-3, added note to Table 10-7 and clarified Section 12.3. Corrected beginning address for On-Chip Data RAM, Table 4-6. Corrected addresses in Table 4-6. Corrected Figure 10-21. Added output voltage maximum value and note to clarify in Table 10-1; also removed overall life expectancy note, since life expectancy is dependent on customer usage and must be determined by reliability engineering. Clarified value and unit measure for Maximum allowed PD in Table 10-3. Corrected note about average value for Flash Data Retention in Table 10-4. Added new RoHS-compliant orderable part numbers in Table 13-1. Updated Table 10-23 to reflect new value for maximum Uncalibrated Gain Error Deleted RSTO from Pin Group 2 (listed after Table 10-1). Deleted formula for Max Ambient Operating Temperature (Automotive) and Max Ambient Operating Temperature (Industrial) in Table 10-4. Added RoHS-compliance and “pb-free” language to back cover. Rev 4.0 Rev 5.0 Rev 6.0 Rev 7.0 Rev 8.0 Rev 9.0 Rev 10.0 Rev 11.0 Rev 12.0 Rev 13.0 Rev 14.0 Please see http://www.freescale.com for the most current Data Sheet revision. 56F8345 Technical Data, Rev. 17 2 Freescale Semiconductor Preliminary Document Revision History (Continued) Version History Rev 15.0 Description of Change Updated JTAG ID in Section 6.5.4. Added information/corrected state during reset in Table 2-2. Clarified external reference crystal frequency for PLL in Table 10-14 by increasing maximum value to 8.4MHz. Replaced “Tri-stated” with an explanation in State During Reset column in Table 2-2. • Added the following note to the description of the TMS signal in Table 2-2: Note: Always tie the TMS pin to VDD through a 2.2K resistor. • Added the following note to the description of the TRST signal in Table 2-2: Note: For normal operation, connect TRST directly to VSS. If the design is to be used in a debugging environment, TRST may be tied to VSS through a 1K resistor. Rev 16.0 Rev. 17 Please see http://www.freescale.com for the most current data sheet revision. 56F8345 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 3 56F8345 Technical Data, Rev. 17 4 Freescale Semiconductor Preliminary 56F8345/56F8145 General Description Note: Features in italics are NOT available in the 56F8145 device. • Up to 60 MIPS at 60MHz core frequency • DSP and MCU functionality in a unified, C-efficient architecture • 128KB Program Flash • 4KB Program RAM • 8KB Data Flash • 8KB Data RAM • 8KB Boot Flash • Up to two 6-channel PWM modules • Four 4-channel, 12-bit ADCs • Temperature Sensor • Up to two Quadrature Decoders • FlexCAN module • Optional On-Chip Regulator • Two Serial Communication Interfaces (SCIs) • Up to two Serial Peripheral Interface (SPIs) • Up to four general-purpose Quad Timers • Computer Operating Properly (COP)/Watchdog • JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging • Up to 49 GPIO lines • 128-pin LQFP Package RSTO RESET 6 PWM Outputs 3 4 Current Sense Inputs or GPIOC Fault Inputs Program Controller and Hardware Looping Unit 5 JTAG/ EOnCE Port VPP 2 VCAP 4 OCR_DIS VDD VSS 7 5 Digital Reg VDDA 2 VSSA PWMA Analog Reg 16-Bit 56800E Core Low Voltage Supervisor Bit Manipulation Unit 6 PWM Outputs 3 4 4 4 5 4 4 Current Sense Inputs or GPIOD Fault Inputs PWMB Address Generation Unit Data ALU 16 x 16 + 36 -->36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators AD0 AD1 VREF PAB PDB CDBR CDBW ADCA Memory Program Memory 64K x 16 Flash 2K x 16 RAM 4K x 16 Boot Flash Data Memory 4K x 16 Flash 4K x 16 RAM XDB2 XAB1 XAB2 PDB CDBR CDBW R/W Control AD0 ADCB AD1 TEMP_SENSE 4 Quadrature Decoder 0 or Quad Timer A or GPIOC Quadrature Decoder 1 or Quad Timer B or SP1I or GPIOC Quad Timer C or GPIOE Quad Timer D or GPIOE FlexCAN System Bus Control External Bus Interface Unit PAB * External Address Bus Switch * External Data Bus Switch * Bus Control 6 5 A8-13 or GPIOA0-5 GPIOB0-4 or A16-20 4 D7-10 or GPIOF0-3 6 GPIOD0-5 or CS2-7 4 IPBus Bridge (IPBB) Peripheral Device Selects 2 4 2 Decoding Peripherals RW Control IPAB IPWDB IPRDB Clock resets P System O Integration R Module PLL * EMI not functional in this package; use as GPIO pins SPI0 or GPIOE 4 SCI1 or GPIOD 2 SCI0 or GPIOE 2 COP/ Interrupt Watchdog Controller O Clock S Generator C XTAL EXTAL IRQA IRQB CLKO CLKMODE 56F8345/56F8145 Block Diagram - 128 LQFP 56F8345 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 5 Table of Contents Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 7 1.1. 1.2. 1.3. 1.4. 1.5. 1.6. 56F8345/56F8145 Features . . . . . . . . . . . . . . 7 Device Description . . . . . . . . . . . . . . . . . . . . . .9 Award-Winning Development Environment . .11 Architecture Block Diagram . . . . . . . . . . . . . . 12 Product Documentation . . . . . . . . . . . . . . . . . 16 Data Sheet Conventions . . . . . . . . . . . . . . . . 16 Part 8: General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . 125 8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 125 8.2. Memory Maps . . . . . . . . . . . . . . . . . . . . . . . 125 8.3. Configuration. . . . . . . . . . . . . . . . . . . . . . . . 125 Part 9: Joint Test Action Group (JTAG) . . 131 9.1. JTAG Information . . . . . . . . . . . . . . . . . . . . 131 Part 2: Signal/Connection Descriptions . . 17 2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Part 10: Specifications. . . . . . . . . . . . . . . . 131 10.1. General Characteristics. . . . . . . . . . . . . . . 131 10.2. DC Electrical Characteristics. . . . . . . . . . . 136 10.3. AC Electrical Characteristics . . . . . . . . . . . 140 10.4. Flash Memory Characteristics. . . . . . . . . . 140 10.5. External Clock Operation Timing . . . . . . . 141 10.6. Phase Locked Loop Timing. . . . . . . . . . . . 141 10.7. Crystal Oscillator Timing . . . . . . . . . . . . . . 142 10.8. Reset, Stop, Wait, Mode Select, and Interrupt Timing . . . . . . . . . . . . . . . 142 10.9. Serial Peripheral Interface (SPI) Timing . . 144 10.10. Quad Timer Timing . . . . . . . . . . . . . . . . . 148 10.11. Quadrature Decoder Timing . . . . . . . . . . 148 10.12. Serial Communication Interface (SCI) Timing . . . . . . . . . . . . . . . . . 149 10.13. Controller Area Network (CAN) Timing . . 150 10.14. JTAG Timing . . . . . . . . . . . . . . . . . . . . . . 150 10.15. Analog-to-Digital Converter (ADC) Parameters . . . . . . . . . . . . 152 10.16. Equivalent Circuit for ADC Inputs . . . . . . 155 10.17. Power Consumption . . . . . . . . . . . . . . . . 156 Part 3: On-Chip Clock Synthesis (OCCS) . . 36 3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.2. External Clock Operation . . . . . . . . . . . . . . . .36 3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Part 4: Memory Map. . . . . . . . . . . . . . . . . . . 38 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.7. 4.8. Introductio . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Map. . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Vector Table . . . . . . . . . . . . . . . . . . Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Map . . . . . . . . . . . . . . . . . . . . EOnCE Memory Map . . . . . . . . . . . . . . . . . . Peripheral Memory Mapped Registers . . . . . Factory Programmed Memory. . . . . . . . . . . . 38 39 41 45 45 46 47 73 Part 5: Interrupt Controller (ITCN) . . . . . . . 74 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. 5.7. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Functional Description . . . . . . . . . . . . . . . . . . 74 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 76 Operating Modes . . . . . . . . . . . . . . . . . . . . . . 76 Register Descriptions . . . . . . . . . . . . . . . . . . .77 Resets . . . . . . . . . . . . . . . . . . . . . .