(56F8135 / 56F8335) 16-bit Digital Signal Controller

www.DataSheet4U.com 56F8335/56F8135 Data Sheet Preliminary Technical Data 56F8300 16-bit Digital Signal Controller MC56F8335 Rev. 1 12/2005 freescale.com Document Revision History Version History Rev. 0 Rev. 1 Initial Release Deleted RSTO from Pin Group 2 (listed after Table 10-1). Deleted formula for Max Ambient Operating Temperature (Automotive) and Max Ambient Operating Temperature (Industrial) in Table 10-4. Added RoHS-compliance and “pb-free” language to back cover. Description of Change Please see http://www.freescale.com for the most current Data Sheet revision. 56F8335 Technical Data, Rev. 1 2 Freescale Semiconductor Preliminary 56F8335/56F8135 General Description Note: Features in italics are NOT available in the 56F8135 device. • Up to 60 MIPS at 60MHz core frequency • DSP and MCU functionality in a unified, C-efficient architecture • 64KB Program Flash • 4KB Program RAM • 8KB Data Flash • 8KB Data RAM • 8KB Boot Flash • Up to two 6-channel PWM modules • Four 4-channel, 12-bit ADCs • Temperature Sensor • Up to two Quadrature Decoders • FlexCAN module • Optional On-Chip Regulator • Two Serial Communication Interfaces (SCIs) • Up to two Serial Peripheral Interface (SPIs) • Up to four general-purpose Quad Timers • Computer Operating Properly (COP)/Watchdog • JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging • Up to 49 GPIO lines • 128-pin LQFP Package RSTO RESET 6 PWM Outputs 3 4 Current Sense Inputs or GPIOC Fault Inputs Program Controller and Hardware Looping Unit VPP 5 JTAG/ EOnCE Port VCAP 4 OCR_DIS VDD VSS 7 5 Digital Reg VDDA 2 VSSA 2 PWMA Analog Reg 16-Bit 56800E Core Low Voltage Supervisor Bit Manipulation Unit 6 PWM Outputs 3 4 4 4 5 4 4 Current Sense Inputs or GPIOD Fault Inputs Address Generation Unit PWMB Data ALU 16 x 16 + 36 -->36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators AD0 ADCA AD1 VREF PAB PDB CDBR CDBW Memory Program Memory 32K x 16 Flash 2K x 16 RAM 4K x 16 Boot Flash Data Memory 4K x 16 Flash 4K x 16 RAM XDB2 XAB1 XAB2 PAB PDB CDBR CDBW R/W Control AD0 ADCB AD1 TEMP_SENSE 4 Quadrature Decoder 0 or Quad Timer A or GPIOC Quadrature Decoder 1 or Quad Timer B or SP1I or GPIOC Quad Timer C or GPIOE Quad Timer D or GPIOE FlexCAN System Bus Control External Bus Interface Unit * External Address Bus Switch 6 5 A8-13 or GPIOA0-5 GPIOB0-4 or A16-20 * External Data Bus Switch 4 D7-10 or GPIOF0-3 * Bus Control 6 GPIOD0-5 or CS2-7 4 IPBus Bridge (IPBB) Peripheral Device Selects RW Control IPAB IPWDB IPRDB 2 Decoding Peripherals 4 2 Clock resets P System O Integration R Module PLL * EMI not functional in this package; use as GPIO pins SPI0 or GPIOE 4 SCI1 or GPIOD 2 SCI0 or GPIOE 2 COP/ Interrupt Watchdog Controller O Clock S Generator C XTAL EXTAL IRQA IRQB CLKO CLKMODE 56F8335/56F8135 Block Diagram - 128 LQFP 56F8335 Technical Data, Rev. 1 Freescale Semiconductor Preliminary 3 Table of Contents Part 1: Overview. . . . . . . . . . . . . . . . . . . . . . . 5 1.1. 1.2. 1.3. 1.4. 1.5. 1.6. 56F8335 Features . . . . . . . . . . . . . . . . . . . . . .5 Device Description . . . . . . . . . . . . . . . . . . . . . .6 Award-Winning Development Environment . . .8 Architecture Block Diagram . . . . . . . . . . . . . . .8 Product Documentation . . . . . . . . . . . . . . . . .11 Data Sheet Conventions . . . . . . . . . . . . . . . .12 Part 8: General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 116 8.2. Memory Maps . . . . . . . . . . . . . . . . . . . . . . . 116 8.3. Configuration . . . . . . . . . . . . . . . . . . . . . . . . 116 Part 9: Joint Test Action Group (JTAG) . 120 9.1. JTAG Information . . . . . . . . . . . . . . . . . . . . . 120 Part 2: Signal/Connection Descriptions . . . 13 2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Part 10: Specifications . . . . . . . . . . . . . . . 121 10.1. General Characteristics . . . . . . . . . . . . . . . 121 10.2. DC Electrical Characteristics. . . . . . . . . . . 125 10.3. AC Electrical Characteristics . . . . . . . . . . . 129 10.4. Flash Memory Characteristics . . . . . . . . . . 130 10.5. External Clock Operation Timing . . . . . . . . 130 10.6. Phase Locked Loop Timing . . . . . . . . . . . . 131 10.7. Crystal Oscillator Timing . . . . . . . . . . . . . . 131 10.8. Reset, Stop, Wait, Mode Select, and Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . 132 10.9. Serial Peripheral Interface (SPI) Timing . . . 134 10.10. Quad Timer Timing . . . . . . . . . . . . . . . . . 137 10.11. Quadrature Decoder Timing . . . . . . . . . . . 137 10.12. Serial Communication Interface (SCI) Timing . . . . . . . . . . . . . . . . . 138 10.13. Controller Area Network (CAN) Timing . . 139 10.14. JTAG Timing . . . . . . . . . . . . . . . . . . . . . . 139 10.15. Analog-to-Digital Converter (ADC) Parameters . . . . . . . . . . . . 141 10.16. Equivalent Circuit for ADC Inputs . . . . . . . 144 10.17. Power Consumption . . . . . . . . . . . . . . . . . 144 Part 3: On-Chip Clock Synthesis (OCCS) . . 30 3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.2. External Clock Operation . . . . . . . . . . . . . . . 30 3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Part 4: Memory Map . . . . . . . . . . . . . . . . . . . 32 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.7. 4.8. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Program Map . . . . . . . . . . . . . . . . . . . . . . . . .33 Interrupt Vector Table . . . . . . . . . . . . . . . . . . .34 Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Flash Memory Map . . . . . . . . . . . . . . . . . . . . 38 EOnCE Memory Map . . . . . . . . . . . . . . . . . . .40 Peripheral Memory Mapped Registers . . . . . 41 Factory Programmed Memory. . . . . . . . . . . . 66 Part 5: Interrupt Controller (ITCN) . . . . . . . . 67 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. 5.7. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Functional Description . . . . . . . . . . . . . . . . . .67 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .69 Operating Modes . . . . . . . . . . . . . . . . . . . . . . 69 Register Descriptions . . . . . . . . . . . . . . . . . . .70 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 Part 11: Packaging . . . . . . . . . . . . . . . . . . 146 11.1. 56F8335 Package and Pin-Out Information 146 Part 12: Design Considerations . . . . . . . . 150 12.1. Thermal Design Considerations . . . . . . . . . 150 12.2. Electrical Design Considerations . . . . . . . . 151 12.3. Power Distribution and I/O Ring Implementation . . . . . . . . . . . . . . . . 152 Part 6: System Integration Module (SIM) . . 96 6.1. 6.2. 6.3. 6.4. 6.5. 6.6. 6.7. 6.8. 6.9. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Operating Modes . . . . . . . . . . . . . . . . . . . . . . 97 Operating Mode Register . . . . . . . . . . . . . . . .97 Register Descriptions . . . . . . . . . . . . . . . . . . .98 Clock Generation Overview . . . . . . . . . . . . .111 Power-Down Modes Overview . . . . . . . . . . .111 Stop and Wait Mode Disable Function . . . . .112 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 Part 13: Ordering Information . . . . . . . . . 153 Part 7: Security Features . . . . . . . . . . . . . . 113 7.1. Operation with Security Enabled . . . . . . . . . 113 7.2. Flash Access Blocking Mechanisms . . . . . . 113 56F8335 Technical Data, Rev. 1 4 Freescale Semiconductor Preliminary 56F8335/56F8135 Features Part 1 Overview 1.1 56F8335/56F8135 Features 1.1.1 • • • • • • • • • • • • • • Core Efficient 16-bit 56800E family controller engine with dual Harvard architecture Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) Four 36-bit accumulators, including extension bits Arithmetic and logic multi-bit shifter Parallel instruction set with unique DSP addressing modes Hardware DO and REP loops Three internal address buses Four internal data buses Instruction set supports both DSP and controller functions Controller-style addressing modes and instructions for compact code Efficient C compiler and local variable support Software subroutine and interrupt stack with depth limited only by memory JTAG/EOnCE debug programming interface 1.1.2 Differences Between Devices Table 1-1 outlines the key differences between the 56F8335 and 56F8135 devices. Table 1-1 Device Differences Feature Guaranteed Speed Program RAM Data Flash PWM CAN Quad Timer Quadrature Decoder Temperature Sensor 56F8335 60MHz/60 MIPS 4KB 8KB 2x6 1 4 2x4 1 56F8135 40MHz/40MIPS Not Available Not Available 1x6 Not Available 2 1x4 Not Available 56F8335 Technical Data, Rev. 1 Freescale Semiconductor Preliminary 5 1.1.3 • • • Memory Harvard architecture permits as many as three simultaneous accesses to program and data memory Flash security protection feature On-chip memory, including a low-cost, high-volume Flash solution — 64KB of Program Flash — 4KB of Program RAM — 8KB of Data Flash — 8KB of Data RAM — 8KB of Boot Flash Note: Features in italics are NOT available in the 56F8135 device. • EEPROM emulation capability 1.1.4 • Peripheral Circuits Pulse Width Modulator module: — In the 56F8335, two Pulse Width Modulator modules, each with six PWM outputs, three Current Sense inputs, and four Fault inputs; fault-tolerant design with dead time insertion; supports both center-aligned and edge-aligned mode