16-bit Digital Signal Controllers

www.DataSheet4U.com 56F8036 Data Sheet Preliminary Technical Data 56F8000 16-bit Digital Signal Controllers MC56F8036 Rev. 3 01/2007 freescale.com Document Revision History Version History Rev. 0 Rev. 1 Initial public release. • In Table 10-4, added an entry for flash data retention with less than 100 program/erase cycles (minimum 20 years). • In Table 10-6, changed the device clock speed in STOP mode from 8MHz to 4MHz. • In Table 10-12, changed the typical relaxation oscillator output frequency in Standby mode from 400kHz to 200kHz. • Changed input propagation delay values in Table 10-21 as follows: Old values: 1 μs typical, 2 μs maximum New values: 35 ns typical, 45 ns maximum Rev. 2 Rev. 3 In Table 10-20, changed the maximum ADC internal clock frequency from 8MHz to 5.33MHz. Added the following note to the description of the TMS signal in Table 2-3: Note: Always tie the TMS pin to VDD through a 2.2K resistor. Description of Change Please see http://www.freescale.com for the most current Data Sheet revision. 56F8036 Data Sheet, Rev. 3 2 Freescale Semiconductor Preliminary 56F8036 General Description • Up to 32 MIPS at 32MHz core frequency • DSP and MCU functionality in a unified, C-efficient architecture • 64KB (32K x 16) Program Flash • 8KB (4K x 16) Unified Data/Program RAM • One 6-channel PWM module clocked at up to 96MHz • Two independent 5-channel 12-bit high-speed Analog-to-Digital Converters (ADCs) • Two internal 12-bit Digital-to-Analog Converters (DACs) • Two Analog Comparators • Three Programmable Interval Timers (PITs) • One Queued Serial Communication Interface (QSCI) with LIN slave functionality RESET or GPIOA 4 • One Queued Serial Peripheral Interface (QSPI) • Freescale’s scalable controller area network (MSCAN) 2.0 A/B Module • One 16-bit Quad Timer clocked at up to 96MHz • One Inter-Integrated Circuit (I2C) port • Computer Operating Properly (COP)/Watchdog • On-Chip Relaxation Oscillator • Integrated Power-On Reset (POR) and Low-Voltage Interrupt (LVI) module • JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging • Up to 39 GPIO lines • 48-pin LQFP Package VCAP 2 VDD 2 VSS 3 VDDA VSSA 11 PWM or TMRA or CMP or GPIOA Program Controller and Hardware Looping Unit JTAG/EOnCE Port or GPIOD Digital Reg Analog Reg 16-Bit 56800E Core Low-Voltage Supervisor Bit Manipulation Unit Address Generation Unit Data ALU 16 x 16 + 36 -> 36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators DAC 5 PAB PDB CDBR CDBW AD0 ADC or CMP or GPIOC AD1 Memory Program Memory 32K x 16 Flash Unified Data / Program RAM 4K x 16 XDB2 XAB1 XAB2 PAB PDB CDBR CDBW R/W Control 5 System Bus Control Programmable Interval Timer IPBus Bridge (IPBB) I2C or CAN or CMP or GPIOB QSPI or PWM or I2C or TMRA or GPIOB 4 QSCI or PWM or I2C or TMRA or GPIOB COP/ Watchdog Interrupt Controller System Integration Module P O R O Clock S Generator* C XTAL, CLKIN, or GPIOD EXTAL or GPIOD 4 3 *Includes On-Chip Relaxation Oscillator 56F8036 Block Diagram 56F8036 Data Sheet, Rev. 3 Freescale Semiconductor Preliminary 3 56F8036 Data Sheet Table of Contents Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 5 1.1. 1.2. 1.3. 1.4. 1.5. 1.6. 56F8036 Features . . . . . . . . . . . . . . . . . . . . . 5 56F8036 Description . . . . . . . . . . . . . . . . . . . 7 Award-Winning Developme . nt Environment 8 Architecture Block Diagram 8 Product Documentation . . . . . . . . . . . . . . . 16 Data Sheet Conventions. . . . . . . . . . . . . . . 16 Part 8: General Purpose Input/Output (GPIO) . . . . . . . . . . . . 114 8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . 114 8.2. Configuration . . . . . . . . . . . . . . . . . . . . . . . 114 8.3. Reset Values . . . . . . . . . . . . . . . . . . . . . . . 117 Part 9: Joint Test Action Group (JTAG) . . 122 9.1. 56F8036 Informatio . . . . . . . . . . . . . . . . .n 122 Part 2: Signal/Connection Descriptions . . 17 2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2. 56F8036 Signal Pins . . . . . . . . . . . . . . . . . 21 Part 10: Specifications . . . . . . . . . . . . . . . .122 10.1. General Characteristics . . . . . . . . . . . . . . 122 10.2. DC Electrical Characteristics . . . . . . . . . . 126 10.3. AC Electrical Characteristics . . . . . . . . . . 129 10.4. Flash Memory Characteristics . . . . . . . . . 129 10.5. External Clock Operation Timing . . . . . . . 130 10.6. Phase Locked Loop Timing . . . . . . . . . . . 131 10.7. Relaxation Oscillator Timing. . . . . . . . . . . 131 10.8. Reset, Stop, Wait, Mode Select, and Interrupt Timing . . . . . . . . . . . . . . 133 10.9. Serial Peripheral Interface (SPI) Timing . 134 10.10. Quad Timer Timing. . . . . . . . . . . . . . . . . 137 10.11. Serial Communication Interface (SCI) Timing. . . . . . . . . . . . . . . . . 138 10.12. Freescale’s Scalable Controller Area Network (MSCAN) Timing . . 139 10.13. Inter-Integrated Circuit Interface (I2C) Timing . . . . . . . . . . . . . . . . 139 10.14. JTAG Timing. . . . . . . . . . . . . . . . . . . . . . 141 10.15. Analog-to-Digital Converter (ADC) Parameters . . . . . . . . . . . . 142 10.16. Equivalent Circuit for ADC Inputs . . . . . . 143 10.17. Comparator (CMP) Parameters . . . . . . . 143 10.18. Digital-to-Analog Converter (DAC) Parameters . . . . . . . . . . . 144 10.19. Power Consumption . . . . . . . . . . . . . . . 145 Part 3: OCCS . . . . . . . . . . . . . . . . . . . . . . . . . 33 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Operating Modes . . . . . . . . . . . . . . . . . . . . 33 Internal Clock Source . . . . . . . . . . . . . . . . . 34 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . 34 Ceramic Resonator . . . . . . . . . . . . . . . . . . . 35 External Clock Input - Crystal Oscillator Option. . . . . . . . . . . . . . 35 3.8. Alternate External Clock Input . . . . . . . . . . . 36 3.1. 3.2. 3.3. 3.4. 3.5. 3.6. 3.7. Part 4: Memory Maps . . . . . . . . . . . . . . . . . 36 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 36 Interrupt Vector Table . . . . . . . . . . . . . . . . . 37 Program Map . . . . . . . . . . . . . . . . . . . . . . . . 39 Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . 40 EOnCE Memory Map . . . . . . . . . . . . . . . . . 41 Peripheral Memory-Mapped Registers . . . . 42 Part 5: Interrupt Controller (ITCN) . . . . . . . 56 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. 5.7. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 56 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Functional Description . . . . . . . . . . . . . . . . . 56 Block Diagram . . . . . . . . . . . . . . . . . . . . . . 58 Operating Modes . . . . . . . . . . . . . . . . . . . . . 59 Register Descriptions . . . . . . . . . . . . . . . . . 59 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Part 11: Packaging . . . . . . . . . . . . . . . . . . .147 11.1. 56F8036 Package and Pin-Out Information . . . . . . . . . . . 147 Part 6: System Integration Module (SIM) . . 79 6.1. 6.2. 6.3. 6.4. 6.5. 6.6. 6.7. 6.8. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 79 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Register Descriptions . . . . . . . . . . . . . . . . . 81 Clock Generation Overview . . . . . . . . . . . . 107 Power-Saving Modes . . . . . . . . . . . . . . . . 108 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 112 Part 12: Design Considerations . . . . . . . . 150 12.1. Thermal Design Considerations . . . . . . . . 150 12.2. Electrical Design Considerations . . . . . . . 151 Part 13: Ordering Information . . . . . . . . . . 152 Part 14: Appendix. . . . . . . . . . . . . . . . . . . . 153 Part 7: Security Features . . . . . . . . . . . . . 112 7.1. Operation with Security Enabled . . . . . . . 112 7.2. Flash Access Lock and Unlock Mechanisms . . . . . . . . . . 113 56F8036 Data Sheet, Rev. 3 4 Freescale Semiconductor Preliminary 56F8036 Features Part 1 Overview 1.1 56F8036 Features 1.1.1 • • • • • • • • • • • • • • Digital Signal Controller Core Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard architecture As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) Four 36-bit accumulators, including extension bits 32-bit arithmetic and logic multi-bit shifter Parallel instruction set with unique DSP addressing modes Hardware DO and REP loops Three internal address buses Four internal data buses Instruction set supports both DSP and controller functions Controller-style addressing modes and instructions for compact code Efficient C compiler and local variable support Software subroutine and interrupt stack with depth limited only by memory JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time debugging 1.1.2 • • • Memory Dual Harvard architecture permits as many as three simultaneous accesses to program and data memory Flash security and protection that prevent unauthorized users from gaining access to the internal Flash On-chip memory — 64KB of Program Flash — 8KB of Unified Data/Program RAM EEPROM emulation capability using Flash • 1.1.3 • Peripheral Circuits for 56F8036 One multi-function six-output Pulse Width Modulator (PWM) module — Up to 96MHz PWM operating clock — 15 bits of resolution — Center-aligned and edge-aligned PWM signal mode — Four programmable fault inputs with programmable digital filter — Double-buffered PWM registers — Each comple