16-bit Digital Signal Controllers

56857 Data Sheet Technical Data www.DataSheet4U.com 56800E 16-bit Digital Signal Controllers DSP56857 Rev. 6 01/2007 freescale.com 56857 General Description • 120 MIPS at 120MHz • 40K x 16-bit Program SRAM • 24K x 16-bit Data SRAM • 1K x 16-bit Boot ROM • Six (6) independent channels of DMA • Two (2) Enhanced Synchronous Serial Interfaces (ESSI) • Two (2) Serial Communication Interfaces (SCI) • Serial Port Interface (SPI) • Four (4) dedicated GPIO • 8-bit Parallel Host Interface • General Purpose 16-bit Quad Timer • JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging • Computer Operating Properly (COP)/Watchdog Timer • Time-of-Day (TOD) • 100 LQFP package • Up to 47 GPIO 6 VDDIO 12 VDD 8 VSSIO 12 VSS VDDA 5 VSSA 2 JTAG/ Enhanced OnCE Program Controller and Hardware Looping Unit Address Generation Unit 16-Bit DSP56800E Core Data ALU 16 x 16 + 36 Æ 36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators Bit Manipulation Unit PAB PDB CDBR CDBW Memory Program Memory 40,960 x 16 SRAM Boot ROM 1024 x 16 ROM Data Memory 24,576 x 16 SRAM XDB2 XAB1 XAB2 PAB PDB CDBR CDBW System Bus Control DMA 6 channel Core CLK IPBus Bridge (IPBB) IPWDB Decoding Peripherals IPRDB IPAB DMA Requests IPBus CLK POR 3 CLKO MODEA-C or (GPIOH0-H2) System COP/TOD CLK Integration Module RSTO RESET EXTAL XTAL CS0-CS3[3:0] used as GPIOA0-A3 GPIO Contol 2 SCI ESSI0 or or GPIOE GPIOC ESSI1 or GPIOD Quad Timer or GPIOG 4 SPI Host Interrupt or Interface Controller GPIOF or GPIOB 4 16 IRQA IRQB COP/ Watchdog Time of Day Clock Generator OSC PLL 4 6 6 56857 Block Diagram 56857 Technical Data, Rev. 6 Freescale Semiconductor 3 Part 1 Overview 1.1 56857 Features 1.1.1 • • • • • • • • • • • • • • • • Digital Signal Processing Core Efficient 16-bit engine with dual Harvard architecture 120 Million Instructions Per Second (MIPS) at 120MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) Four (4) 36-bit accumulators including extension bits 16-bit bidirectional shifter Parallel instruction set with unique DSP addressing modes Hardware DO and REP loops Three (3) internal address buses Four (4) internal data buses Instruction set supports both DSP and controller functions Four (4) hardware interrupt levels Five (5) software interrupt levels Controller-style addressing modes and instructions for compact code Efficient C Compiler and local variable support Software subroutine and interrupt stack with depth limited only by memory JTAG/Enhanced OnCE debug programming interface 1.1.2 • • Memory Harvard architecture permits up to three (3) simultaneous accesses to program and data memory On-Chip Memory — 40K × 16-bit Program RAM — 24K × 16-bit Data RAM — 1K × 16-bit Boot ROM — Chip Select Logic used as dedicated GPIO 1.1.3 • • • • • • • Peripheral Circuits for 56857 General Purpose 16-bit Quad Timer* Two Serial Communication Interfaces (SCI)* Serial Peripheral Interface (SPI) Port* Two (2) Enhanced Synchronous Serial Interface (ESSI) modules* Computer Operating Properly (COP)/Watchdog Timer JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, real-time debugging Six (6) independent channels of DMA 56857 Technical Data, Rev. 6 4 Freescale Semiconductor 56857 Description • • • 8-bit Parallel Host Interface* Time of Day Up to 47 GPIO * Each peripheral I/O can be used alternately as a General Purpose I/O if not needed 1.1.4 • • Energy Information Fabricated in high-density CMOS with 3.3V, TTL-compatible digital inputs Wait and Stop modes available 1.2 56857 Description The 56857 is a member of the 56800E core-based family of controllers. It combines, on a single chip, the processing power of a Digital Signal Processor (DSP) and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56857 is well-suited for many applications. The 56857 includes many peripherals that are especially useful for low-end Internet appliance applications and low-end client applications such as telephony; portable devices; Internet audio; and point-of-sale systems, such as noise suppression; ID tag readers; sonic/subsonic detectors; security access devices; remote metering; sonic alarms. The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C Compilers, enabling rapid development of optimized control applications. The 56857 supports program execution from either internal or external memories. Two data operands can be accessed from the on-chip Data RAM per instruction cycle. The 56857 also provides two external dedicated interrupt lines, and up to 47 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. The 56857 controller includes 40K words of Program RAM, 24K words of Data RAM and 1K of Boot ROM. This controller also provides a full set of standard programmable peripherals that include 8-bit parallel Host Interface, Two Enhanced Synchronous Serial Interfaces (ESSI), one Serial Peripheral Interface (SPI), two Serial Communications Interfaces (SCI), and one Quad Timer. The ESSIs, SPI, SCIs IO and Quad Timer can be used as General Purpose Input/Outputs when its primary function is not required. 56857 Technical Data, Rev. 6 Freescale Semiconductor 5 1.3 State of the Art Development Environment • • Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system. The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development. 1.4 Product Documentation The four documents listed in Table 1-1 are required for a complete description of and proper design with the 56857. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, or online at www.freescale.com. Table 1-1 56857 Chip Documentation Topic 56800E Reference Manual DSP56857 User’s Manual DSP56857 Technical Data Sheet DSP56857 Errata Description Detailed description of the 56800E architecture, 16-bit core processor and the instruction set Detailed description of memory, peripherals, and interfaces of the 56857 Electrical and timing specifications, pin descriptions, and package descriptions (this document) Details any chip issues that might be present Order Number 56800ERM DSP5685xUM DSP56857 DSP56857E 1.5 Data Sheet Conventions This data sheet uses the following conventions: OVERBAR “asserted” “deasserted” Examples: This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low. A high true (active high) signal is high or a low true (active low) signal is low. A high true (active high) signal is low or a low true (active low) signal is high. Signal/Symbol PIN PIN PIN PIN Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage1 VIL/VOL VIH/VOH VIH/VOH VIL/VOL 1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. 56857 Technical Data, Rev. 6 6 Freescale Semiconductor Introduction Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56857 are organized into functional groups, as shown in Table 2-1 and as illustrated in Figure 2-1. In Table 3-1 each table row describes the package pin and the signal or signals present. Table 2-1 Functional Group Pin Allocations Functional Group Power (VDD, VDDIO, or VDDA) Ground (VSS, VSSIO,or VSSA) PLL and Clock Chip Select Logic used as dedicated GPIO Interrupt and Program Control Host Interface (HI)* Enhanced Synchronous Serial Interface (ESSI0) Port* Enhanced Synchronous Serial Interface (ESSI1) Port* Serial Communications Interface (SCI0) Ports* Serial Communications Interface (SCI1) Ports* Serial Peripheral Interface (SPI) Port* Quad Timer Module Port* JTAG/Enhanced On-Chip Emulation (EOnCE) *Alternately, GPIO pins 1. VDD = VDD CORE, VSS = VSS CORE, VDDIO= VDD IO, VSSIO = VSS IO, VDDA = VDD ANA, VSSA = VSS ANA 2. MODE A, MODE B and MODE C can be used as GPIO after the bootstrap process has completed. 3. The following Host Interface signals are multiplexed: HRWB to HRD, HDS to HWR, HREQ to HTRQ and HACK to HRRQ. Number of Pins (8, 12, 1)1 (5, 12, 2)1 3 4 72 163 6 6 2 2 4 4 6 56857 Technical Data, Rev. 6 Freescale Semiconductor 7 Logic Power VDD VSS 8 5 1 1 RXDO (GPIOE0) TXDO (GPIOE1) RXD1 (GPIOE2) TXD1 (GPIOE3) SCI 2 SCI 0 1 I/O Power Analog Power1 VDDIO VSSIO VDDA VSSA 12 12 1 1 2 1 1 1 1 1 STD0 (GPIOC0) SRD0 (GPIOC1) SCK0 (GPIOC2) SC00 (GPIOC3) SC01 (GPIOC4) SC02 (GPIOC5) ESSI 0 56857 1 1 1 1 1 Chip Select CS0 - CS3 (GPIOA0 - A3) 4 1 1 STD1 (GPIOD0) SRD1 (GPIOD1) SCK1 (GPIOD2) SC10 (GPIOD3) SC11 (GPIOD4) SC12 (GPIOD5) ESSI 1 HD0 - HD7 (GPIOB0 - B7) HA0 - HA2 (GPIOB8 - B10) HRWB (HRD) (GPIOB11) Host Interface HDS (HWR) (GPIOB12) HCS (GPIOB13) HREQ (HTRQ) (GPIOB14) HACK (HRRQ) (GPIOB15) Timer Module 8 3 1 1 1 1 1 1 1 1 1 MISO (GPIOF0) MOSI (GPIOF1) SCK (GPIOF2) SS (GPIOF3) SPI 1 1 XTAL EXTAL CLKO PLL / Clock TIO0 - TIO3 (GPIOG0 - G3) 4 1 IRQA IRQB Interrupt / Program Control MODE A, MODE B, MODE C (GPIOH0 - H2) RESET RSTO