Low Voltage 16-Bit D Flip-Flop

www.DataSheet4U.com 54LCX16374 Low Voltage 16-Bit D Flip-Flop with 5V Tolerant Inputs and Outputs July 1999 54LCX16374 Low Voltage 16-Bit D Flip-Flop with 5V Tolerant Inputs and Outputs General Description The LCX16374 contains sixteen non-inverting D flip-flops with TRI-STATE ® outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and Output Enable (OE) are common to each byte and can be shorted together for full 16-bit operation. The LCX16374 is designed for low voltage (3.3V) VCC applications with capability of interfacing to a 5V signal environment. The LCX16374 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. Features 5V tolerant inputs and outputs Power down high impedance inputs and outputs Supports live insertion/withdrawal 2.0V–3.6V VCC supply operation ± 24 mA output drive Implements patented noise/EMI reduction circuitry Functionally compatible with the 54 series 16374 ESD performance: Human body model > 2000V Machine model > 200V n Standard Microcircuit Drawing (SMD) 5962-99535 n n n n n n n n Ordering Code Order Number 54LCX16374W-QML Package Number WA48A Package Description 48-Lead Ceramic Flatpack Logic Symbol Connection Diagram Pin Assignment for Cerpack DS101199-1 Pin Descriptions Pin Names OEn CPn I0–I15 O0–O15 Output Enable Input (Active Low) Clock Pulse Input Inputs Outputs Description DS101199-2 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS101199 www.national.com Functional Description The LCX16374 consists of sixteen edge-triggered flip-flops with individual D-type inputs andTRI-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each byte has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operation of the OEn input does not affect the state of the flip-flops. Inputs CP2 OE2 L L L X L H I8–I15 H L X X Inputs CP1 OE1 L L L X L H I0–I7 H L X X Outputs O0–O7 H L O0 Z Outputs O8–O15 H L O0 Z H = High Voltage Level L = Low Voltage Level X = Immaterial Z = High Impedance O0 = Previous O0 before HIGH to LOW of CP Logic Diagrams Byte 1 (0:7) DS101199-3 Byte 2 (8:15) DS101199-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Voltage (VI) DC Input Diode Current (IIK) VI < GND DC Output Diode Current (IOK) VO < GND VO ≥ VCC DC Output Voltage (VO) (Note 2) Output in High or Low State Output in TRI-STATE DC Output Source or Sink Current (IO) DC VCC or Ground Current Storage Temperature Range (TSTG) Power Dissapation Junction Temperature (TJ) -0.5V to VCC + 0.5V -0.5V to 7.0V −50mA +50mA −50 mA −0.5V to +7.0V −0.5V to +7.0V Recommended Operating Conditions (Note 3) Supply Voltage (VCC) Operating Data Retention Input Voltage (VI) Output Voltage (VO) High or Low State TRI-STATE Operating Temperature (TA) Minimum Input Edge Rate (∆t/∆V) VIN from 0.8V to 2.0V, VCC = 3.0V 0ns/V to 10ns/V Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: IO Absolute Maximum Rating must be observed. Note 3: Unused inputs must be held HIGH or LOW. They may not float. 2.0V to 3.6V 1.5V to 3.6V 0V to 5.5V 0V to VCC 0V to 5.5V −55˚C to +125˚C ± 50mA ± 100mA −65˚C to +150˚C 750mW 175˚C DC Electrical Characteristics Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH = −100 µA IOH = −12 mA IOH = −12 mA IOH = −24 mA IOL = 100 µA IOL = 12 mA IOL = 24 mA II IOZ IOFF ICC ∆ICC Input Leakage Current 3-STATE Output Leakage Power-Off Leakage Current Quiescent Supply Current Increase in ICC per Input 0 ≤ VI ≤ 5.5V 0 ≤ VO ≤ 5.5V VI = VIH or VIL VI or VO = 5.5V VI = VCC or GND 3.6V ≤ VI, VO ≤ 5.5V VIH = VCC −0.6V Conditions VCC (V) 2.7–3.6 2.7–3.6 2.7–3.6 2.7 3.0 3.0 2.7–3.6 2.7 3.0 2.7–3.6 2.7–3.6 0 2.7–3.6 2.7–3.6 2.7–3.6 VCC − 0.2 2.2 2.4 2.2 0.2 0.4 0.55 TA = −55˚C to +125˚C Min 2.0 0.8 Max V V V V V V V V V µA µA µA µA µA µA Units VOL LOW Level Output Voltage ± 5.0 ± 5.0 10 20 ± 20 500 3 www.national.com AC Electrical Characteristics Symbol fMAX tPHL tPLH tPZL tPZH tPLZ tPHZ tS tH tW tOSHL tOSLH Setup Time Hold Time Pulse Width Output to Output Skew (Note 4) Output Disable Time Parameter Maximum Clock Frequency Propagation Delay CP to On Output Enable Time TA = −55˚C to +125˚C, CL = 50pF, RL = 500Ω VCC = 3.3V ± 0.3V VCC = 2.7V Min 200 0.5 0.5 0.5 0.5 1.0 1.0 3.5 2.0 4.0 1.0 1.0 6.5 6.5 6.5 6.5 6.5 6.5 Max Min 200 1.0 1.0 1.0 1.0 1.0 1.0 3.5 2.0 4.0 1.0 1.0 7.0 7.0 7.0 7.0 7.0 7.0 ns ns ns ns ns ns Max MHz ns Units Note 4: Skew is defined as the absolute value of the difference between the actual propagation delay for any two seperate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by design. Dynamic Switching Characteristics Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL Conditions CL = 50 pF, VIH = 3.3V, VIL = 0V CL = 50 pF, VIH = 3.3V, VIL = 0V VCC (V) 3.3 3.3 TA = 25˚C Max 1.2 -1.1 Units V V Capacitance Symbol CIN COUT CPD Parameter Input Capacitance Output Capacitance Power Dissipation Capacitance Conditions VCC = Open, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC, f = 10 MHz Max 10 12 40 Units pF pF pF www.national.com 4 54LCX16374 Low Voltage 16-Bit D Flip-Flop with 5V Tolerant Inputs and Outputs Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Ceramic Flatpack Package Number WA48A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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