Low Voltage 16-Bit Transparent Latch

www.DataSheet4U.com June 1999 54LCX16373 Low Voltage 16-Bit Transparent Latch with 5V Tolerant Inputs and Outputs 54LCX16373 Low Voltage 16-Bit Transparent Latch with 5V Tolerant Inputs and Outputs General Description The LCX16373 contains sixteen non-inverting latches with TRI-STATE ® outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable (LE) is HIGH. When LE is low, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in TRI-STATE. The LCX16373 is designed for low voltage (3.3V) VCC applications with capability of interfacing to a 5V signal environment. The LCX16373 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. Features n n n n n n n n 5V tolerant inputs and outputs Power down high impedance inputs and outputs Supports live insertion/withdrawal 2.0V–3.6V VCC supply operation ± 24 mA output drive Implements patented noise/EMI reduction circuitry Functionally compatible with the 54 series 16373 ESD performance: Human body model > 2000V Machine model > 200V n Standard Microcircuit Drawing (SMD) 5962-9953401 Ordering Code Order Number 54LCX16373W-QML Package Number WA48A Package Description 48-Lead Ceramic Flatpack Logic Symbol Connection Diagram Pin Assignment for Cerpack DS101200-1 Pin Descriptions Pin Names OEn LEn I0–I15 O0–O15 Description Output Enable Input (Active Low) Latch Enable Input Inputs Outputs DS101200-2 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 2001 National Semiconductor Corporation DS101200 www.national.com 54LCX16373 Functional Description The LCX16373 contains sixteen D-type latches with TRI-STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the In enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its I input changes. When LEn is LOW, the latches store information that was present on the I inputs a setup time preceding the HIGH-to-LOW transition of LEn. The TRI-STATE standard outputs are controlled by the Output Enable (OEn) input. When OEn is LOW, the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. LE1 X H H L Inputs OE1 H L L L Inputs LE2 X H H L OE2 H L L L I8–I15 X L H X I0–I7 X L H X Outputs O0–O7 Z L H O0 Outputs O8–O15 Z L H O0 H = High Voltage Level L = Low Voltage Level X = Immaterial Z = High Impedance O0 = Previous O0 before HIGH to LOW transition of Latch Enable Logic Diagrams DS101200-3 DS101200-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 54LCX16373 Absolute Maximum Ratings (Note 1) Supply Voltage (VCC) DC Input Voltage (VI) DC Input Diode Current (IIK) VI < GND DC Output Diode Current (IOK) VO < GND VO ≥ VCC DC Output Voltage (VO) (Note 2) Output in High or Low State Output in TRI-STATE DC Output Source or Sink Current (IO) DC VCC or Ground Current Storage Temperature Range (TSTG) Power Dissapation Junction Temperature (TJ) −0.5V to +7.0V −0.5V to +7.0V −50 mA −50mA +50mA -0.5V to VCC + 0.5V -0.5V to 7.0V Recommended Operating Conditions (Note 3) Supply Voltage (VCC) Operating Data Retention Input Voltage (VI) Output Voltage (VO) High or Low State TRI-STATE Operating Temperature (TA) Minimum Input Edge Rate (∆t/∆V) VIN from 0.8V to 2.0V, VCC = 3.0V 2.7V to 3.6V 1.5V to 3.6V 0V to 5.5V 0V to VCC 0V to 5.5V −55˚C to +125˚C 0ns/V to 10ns/V ± 50mA ± 400mA −65˚C to +150˚C 750mW 175˚C Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: IO Absolute Maximum Rating must be observed. Note 3: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH = −100 µA IOH = −12 mA IOH = −12 mA IOH = −24 mA VOL LOW Level Output Voltage IOL = 100 µA IOL = 12 mA IOL = 24 mA II IOZ IOFF ICC ∆ICC Input Leakage Current TRI-STATE Output Leakage Power-Off Leakage Current Quiescent Supply Current Increase in ICC per Input 0 ≤ VI ≤ 5.5V 0 ≤ VO ≤ 5.5V VI = VIH or VIL VI or VO = 5.5V VI = VCC or GND 3.6V ≤ VI, VO ≤ 5.5V VIH = VCC −0.6V 0 2.7–3.6 2.7–3.6 2.7–3.6 10 20 µA µA µA µA Conditions VCC (V) 2.7–3.6 2.7–3.6 2.7–3.6 2.7 3.0 3.0 2.7–3.6 2.7 3.0 2.7–3.6 2.7–3.6 VCC − 0.2 2.2 2.4 2.2 0.2 0.4 0.55 TA = −55˚C to +125˚C Min 2.0 0.8 Max V V V V V V V V V µA µA Units ± 5.0 ± 5.0 ± 20 500 3 www.national.com 54LCX16373 AC Electrical Characteristics Symbol Parameter Min tPHL tPLH tPHL tPLH tPZL tPZH tPLZ tPHZ tS tH tW tOSHL tOSLH Setup Time, In to LE Hold Time, In to LE LE Pulse Width Output to Output Skew (Note 4) Output Disable Time Propagation Delay In to On Propagation Delay LE to On Output Enable Time 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 2.5 2.0 3.5 1.0 1.0 TA = −55˚C to +125˚C, CL = 50pF, RL = 500Ω VCC = 3.3V ± 0.3V Max 6.0 6.0 6.5 6.5 6.5 6.5 6.5 6.5 Min 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.5 2.0 3.5 1.0 1.0 VCC = 2.7V Max 6.5 6.5 7.0 7.0 7.0 7.0 7.0 7.0 ns ns ns ns ns ns ns ns Units Note 4: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by design. Dynamic Switching Characteristics Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL Conditions CL = 50 pF, VIH = 3.3V, VIL = 0V CL = 50 pF, VIH = 3.3V, VIL = 0V VCC (V) 3.3 3.3 TA = 25˚C Max 1.2 -1.1 V V Units Capacitance Symbol CIN COUT CPD Parameter Input Capacitance Output Capacitance Power Dissipation Capacitance Conditions VCC = Open, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC, f = 10 MHz Max 10 12 40 Units pF pF pF www.national.com 4 54LCX16373 Low Voltage 16-Bit Transparent Latch with 5V Tolerant Inputs and Outputs Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Ceramic Flatpack Package Number WA48A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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