10-Bit D Flip-Flop

www.DataSheet4U.com 54AC821 • 54ACT821 10-Bit D Flip-Flop with TRI-STATE Outputs August 1998 54AC821 • 54ACT821 10-Bit D Flip-Flop with TRI-STATE ® Outputs General Description The ’AC/’ACT821 is a 10-bit D flip-flop with TRI-STATE outputs arranged in a broadside pinout. The ’AC/’ACT821 is functionally identical to the AM29821. n n n n Noninverting outputs Outputs source/sink 24 mA ’ACT821 has TTL-compatible inputs Standard Microcircuit Drawing (SMD) — ’ACT821: 5962-88705 — ’AC821: 5962-91606 Features n TRI-STATE outputs for bus interfacing Logic Symbols Connection Diagrams Pin Assignment for DIP and Flatpak DS100355-1 IEEE/IEC DS100355-3 Pin Assignment for LCC DS100355-2 Pin Names D0–D9 O0–O9 OE CP Description Data Inputs Data Outputs Output Enable Input Clock Input DS100355-4 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT ® is a registered trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100355 www.national.com Functional Description The ’AC/’ACT821 consists of ten D-type edge-triggered flip-flops. The buffered Clock (CP) and buffered Output Enable (OE) are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition. With OE LOW the contents of the flip-flops are available at the outputs. When OE is HIGH the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. The ’AC/’ACT821 is functionally and pin compatible with the AM29821. Function Table Inputs OE H H L L CP N N N N Internal D L H L H Q L H L H Outputs O Z Z L H Function High Z High Z Load Load H = HIGH Voltage Level L = LOW Voltage Level Z = HIGH Impedance N = LOW-to-HIGH Clock Transition Logic Diagram DS100355-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V Recommended Operating Conditions Supply Voltage (VCC) ’AC ’ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54AC/ACT Minimum Input Edge Rate (∆V/∆t) ’AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (∆V/∆t) ’ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns ±50 mA ±50 mA −65˚C to +150˚C 175˚C 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications. DC Characteristics for ’AC Family Devices Symbol VIH Parameter Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage VOH Minimum High Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 54AC TA = −55˚C to +125˚C Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 (Note 2) VIN = VIL or VIH IOH = −12 mA V IOH = −24 mA IOH = −24 mA IOUT = 50 µA V IOUT = −50 µA V VOUT = 0.1V or VCC − 0.1V V VOUT = 0.1V or VCC − 0.1V Units Conditions 3.0 4.5 5.5 VOL Maximum Low Level Output Voltage 3.0 4.5 5.5 2.4 3.7 4.7 0.1 0.1 0.1 V 3.0 4.5 5.5 IIN IOZ Maximum Input Leakage Current Maximum TRI-STATE Current 5.5 5.5 0.50 0.50 0.50 V µA (Note 2) VIN = VIL or VIH IOL = 12 mA IOL = 24 mA IOL = 24 mA VI = VCC, GND VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND ±1.0 ±10.0 µA 3 www.national.com DC Characteristics for ’AC Family Devices Symbol IOLD IOHD ICC (Note 3) Minimum Dynamic Output Current Maximum Quiescent Supply Current Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. (Continued) Parameter VCC (V) 5.5 5.5 5.5 54AC TA = −55˚C to +125˚C Guaranteed Limits 50 −50 160.0 Units mA mA µA Conditions VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ICC for 54AC @ 25˚C is identical to 74AC @ 25˚C. DC Characteristics for ’ACT Family Devices Symbol VIH VIL VOH Parameter Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 54ACT TA = −55˚C to +125˚C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 (Note 5) VIN = VIL or VIH IOH = −24 mA IOH = −24 mA IOUT = 50 µA (Note 5) VIN = VIL or VIH IOL = 24 mA IOL = 24 mA VI = VCC, GND VI = VIL, VIH VO = VCC, GND VI = VCC − 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND V V V VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA Units Conditions 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 3.70 4.70 0.1 0.1 V V 4.5 5.5 IIN IOZ ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum TRI-STATE Current Maximum ICC/Input (Note 6) Minimum Dynamic Output Current Maximum Quiescent Supply Current Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. Note 7: ICC for 54ACT @ 25˚C is identical to 74ACT @ 25˚C. 0.50 0.50 V µA µA mA mA mA µA 5.5 5.5 5.5 5.5 5.5 5.5 ±1.0 ±10.0 1.6 50 −50 160.0 www.national.com 4 AC Electrical Characteristics Symbol Parameter VCC (V) (Note 8) fmax tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum Clock Frequency Propagation Delay CP to On Propagation Delay CP to On Output Enable Time OE to On Output Enable Time OE to On Output Disable Time OE to On Output Disable Time OE to On Note 8: Voltage Range 3.3 is 3.3V ±0.3V Note 9: Voltage Range 5.0 is 5.0V ±0.5V 54AC TA = −55˚C to +125˚C CL = 50 pF Min 95 100 1.0 1.5 1.0 1.5 1.0 1.5 1.0 1.5 1.0 1.5 1.0 1.5 13.0 9.5 13.0 9.5 13.0 9.5 13.0 9.5 12.0 10.0 12.0 10.0 Max Units Fig. No. 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 MHz ns ns ns ns ns ns AC Operating Requirements Symbol Parameter VCC (V) (Note 10) ts th tw Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP CP Pulse Width HIGH or LOW Note 10: Voltage Range 3.3 is 3.3V ±0.3V Note 11: Voltage Range 5.0 is 5.0V ±0.5V 54AC TA = −55˚C to +125˚C CL = 50 pF Guaranteed Minimum 3.0 3.0 3.0 3.0 6.0 5.0 Units Fig. No. 3.3 5.0 3.3 5.0 3.3 5.0 ns ns ns AC Electrical Characteristics VCC Symbol Parameter (V) (Note 12) Min fmax tPLH tPHL tPZH Maximum Clock Frequency Propagation Delay CP to On Propagation Delay CP to On Output Enable Time OE to On 5.0 1.5 12.5 ns 5.0 1.5 11.5 ns 5.0 1.5 11.5 ns 5.0 85 54ACT TA = −55˚C to +125˚C CL = 50 pF Max MHz Units Fig. No. 5 www.national.com AC Electrical Characteristics (Continued) 54ACT TA = −55˚C to +125˚C CL = 50 pF Min Max 13.0 13.5 12.5 ns ns ns 1.5 1.5 1.5 Units VCC Symbol Parameter (V) (Note 12) tPZL tPHZ tPLZ Output Enable Time OE to On Output Disable Time OE to On Output Disable Time OE to On Note 12: Voltage Range 5.0 is 5.0V ±0.5V Fig. No. 5.0 5.0 5.0 AC Operating Requirements VCC Symbol Parameter (V) (Note 13) ts th tw Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP CP Pulse Width HIGH or LOW Note 13: Voltage Range 5.0 is 5.0V ±0.5V 54ACT TA = −55˚C to +125˚C CL = 50 pF Guaranteed Minimum 4.0 3.0 6.0 Units Fig. No. 5.0 5.0 5.0 ns ns ns Capacitance Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 35.0 Units pF pF Conditions VCC = OPEN VCC = 5.0V www.national.com 6 Physical Dimensions inches (millimeters) unless otherwise noted 28 Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E28A 24 Lead Slim (0.300" Wide) Ceramic Dual-In-Line Package (SD) NS Package Number J24F 7 www.national.com 54AC821 • 54ACT821 10-Bit D Flip-Flop with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24 Lead Ceramic Flatpak (F) NS Package Number W24C LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Custome