Octal D Flip-Flop

www.DataSheet4U.com 54AC377 • 54ACT377 Octal D Flip-Flop with Clock Enable February 1999 54AC377 • 54ACT377 Octal D Flip-Flop with Clock Enable General Description The ’AC/’ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation. n Ideal for addressable register applications n Clock enable for address and data synchronization applications n Eight edge-triggered D flip-flops n Buffered common clock n Outputs source/sink 24 mA n See ’273 for master reset version n See ’373 for transparent latch version n See ’374 for TRI-STATE ® version n ’ACT377 has TTL-compatible inputs n Standard Microcircuit Drawing (SMD) — ’AC377: 5962-88702 — ’ACT377: 5962-87697 Features n ICC reduced by 50% Logic Symbols IEEE/IEC DS100290-1 DS100290-2 Pin Names D0–D7 CE Q0–Q7 CP Description Data Inputs Clock Enable (Active LOW) Data Outputs Clock Pulse Input TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT ® is a registered trademark of Fairchild Semiconductor Corporation. © 1999 National Semiconductor Corporation DS100290 www.national.com Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC DS100290-4 DS100290-3 Mode Select-Function Table Operating Mode CP Load ‘1’ Load ‘0’ Hold (Do Nothing) N N N Inputs CE L L H H Dn H L X X Outputs Qn H L No Change No Change X H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial N = LOW-to-HIGH Clock Transition Logic Diagram DS100290-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V Recommended Operating Conditions Supply Voltage (VCC) ’AC ’ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54AC/ACT Minimum Input Edge Rate (∆V/∆t) ’AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (∆V/∆t) ’ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns ±50 mA ±50 mA −65˚C to +150˚C 175˚C 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications. Note 2: See individual datasheets for those devices which differ from the typical input rise and fall times noted here. DC Characteristics for ’AC Family Devices Symbol Parameter VCC (V) VIH Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage VOH Minimum High Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 54AC TA = −55˚C to +125˚C Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 (Note 3) VIN = VIL or VIH IOH = −12 mA V IOH = −24 mA IOH = −24 mA IOUT = 50 µA V IOUT = −50 µA V VOUT = 0.1V or VCC − 0.1V V VOUT = 0.1V or VCC − 0.1V Units Conditions 3.0 4.5 5.5 VOL Maximum Low Level Output Voltage 3.0 4.5 5.5 2.4 3.7 4.7 0.1 0.1 0.1 V 3.0 4.5 5.5 IIN Maximum Input Leakage Current 5.5 0.50 0.50 0.50 V µA (Note 3) VIN = VIL or VIH IOL = 12 mA IOL = 24 mA IOL = 24 mA VI = VCC, GND ±1.0 3 www.national.com DC Characteristics for ’AC Family Devices Symbol Parameter VCC (V) IOLD IOHD ICC (Note 4) Minimum Dynamic Output Current Maximum Quiescent Supply Current Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. (Continued) 54AC TA = −55˚C to +125˚C Guaranteed Limits 50 −50 80.0 Units Conditions 5.5 5.5 5.5 mA mA µA VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ICC for 54AC @ 25˚C is identical to 74AC @ 25˚C. DC Characteristics for ’ACT Family Devices Symbol Parameter VCC (V) VIH VIL VOH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage 4.5 5.5 4.5 5.5 4.5 5.5 54ACT TA = −55˚C to +125˚C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 (Note 6) VIN = VIL or VIH IOH = −24 mA IOH = −24 mA IOUT = 50 µA (Note 6) VIN = VIL or VIH IOL = 24 mA IOL = 24 mA VI = VCC, GND VI = VCC − 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND V V V VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA Units Conditions 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 3.70 4.70 0.1 0.1 V V 4.5 5.5 IIN ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum ICC/Input (Note 7) Minimum Dynamic Output Current Maximum Quiescent Supply Current Note 6: *All outputs loaded; thresholds on input associated with output under test. Note 7: †Maximum test duration 2.0 ms, one output loaded at a time. Note 8: ICC for 54ACT @ 25˚C is identical to 74ACT @ 25˚C. 0.50 0.50 V µA mA mA mA µA 5.5 5.5 5.5 5.5 5.5 ±1.0 1.6 50 −50 80.0 www.national.com 4 AC Electrical Characteristics VCC Symbol Parameter (V) (Note 9) Min fmax tPLH tPHL Maximum Clock Frequency Propagation Delay CP to Qn Propagation Delay CP to Qn Note 9: Voltage Range 3.3 is 3.3V ±0.3V Voltage Range 5.0 is 5.0V ±0.5V 54AC TA = −55˚C to +125˚C CL = 50 pF Max MHz 14.0 10.0 15.0 11.0 ns ns 75 95 1.0 1.5 1.0 1.5 Units Fig. No. 3.3 5.0 3.3 5.0 3.3 5.0 AC Operating Requirements VCC Symbol Parameter (V) (Note 10) 54AC TA = −55˚C to +125˚C CL = 50 pF Guaranteed Minimum ts th ts th tw Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP Setup Time, HIGH or LOW CE to CP Hold Time, HIGH or LOW CE to CP CP Pulse Width HIGH or LOW Note 10: Voltage Range 3.3 is 3.0V ±0.3V Voltage Range 5.0 is 5.0V ±0.5V Fig. Units No. 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 7.5 6.0 1.5 2.5 9.5 6.0 1.0 2.0 6.5 5.0 ns ns ns ns ns AC Electrical Characteristics VCC Symbol Parameter (V) (Note 11) Min fmax tPLH tPHL Maximum Clock Frequency Propagation Delay CP to Qn Propagation Delay CP to Qn Note 11: Voltage Range 5.0 is 5.0V ±0.5V 54ACT TA = −55˚C to +125˚C CL = 50 pF Max MHz 11.0 12.0 ns ns 85 1.5 1.5 Units Fig. No. 5.0 5.0 5.0 5 www.national.com AC Operating Requirements VCC Symbol Parameter (V) (Note 12) 54ACT TA = −55˚C to +125˚C CL = 50 pF Guaranteed Minimum ts th ts th tw Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP Setup Time, HIGH or LOW CE to CP Hold Time, HIGH or LOW CE to CP CP Pulse Width HIGH or LOW Note 12: Voltage Range 5.0 is 5.0V ±0.5V Fig. Units No. 5.0 5.0 5.0 5.0 5.0 7.0 1.0 7.0 1.0 5.5 ns ns ns ns ns Capacitance Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 90.0 Units pF pF Conditions VCC = OPEN VCC = 5.0V www.national.com 6 Physical Dimensions inches (millimeters) unless otherwise noted 20 Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A 20 Lead Ceramic Dual-In-Line Package (D) NS Package Number J20A 7 www.national.com 54AC377 • 54ACT377 Octal D Flip-Flop with Clock Enable Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20 Lead Ceramic Flatpak (F) NS Package Number W20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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