8-Input Universal Shift/Storage Register

www.DataSheet4U.com 54ACC299 • 54ACT299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins September 1998 54AC299 • 54ACT299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins General Description The ’AC/’ACT299 is an 8-bit universal shift/storage register with TRI-STATE ® outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Additional outputs are provided for flip-flops Q0, Q7 to allow easy serial cascading. A separate active LOW Master Reset is used to reset the register. n Common parallel I/O for reduced pin count n Additional serial inputs and outputs for expansion n Four operating modes: shift left, shift right, load and store n TRI-STATE outputs for bus-oriented applications n Outputs source/sink 24 mA n ’ACT299 has TTL-compatible inputs n Standard Microcircuit Drawing (SMD) ’AC299: 5962-88754 ’ACT299: 5962-88771 Features n ICC and IOZ reduced by 50% Ordering Code: Logic Symbols Connection Diagrams Pin Assignment for DIP and Flatpak DS100252-1 IEEE/IEC DS100252-2 Pin Assignment for LCC DS100252-3 DS100252-4 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT ® is a registered trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100252 www.national.com Connection Diagrams Pin Names CP DS0 DS7 S0, S1 MR OE1, OE2 I/O0–I/O7 Q0, Q7 (Continued) Description Clock Pulse Input Serial Data Input for Right Shift Serial Data Input for Left Shift Mode Select Inputs Asynchronous Master Reset TRI-STATE Output Enable Inputs Parallel Data Inputs or TRI-STATE Parallel Outputs Serial Outputs Functional Description The ’AC/’ACT299 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1, as shown in the Truth Table. All flip-flop outputs are brought out through TRI-STATE buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A LOW signal on MR overrides the Select and CP inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed. A HIGH signal on either OE1 or OE2 disables the TRI-STATE buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The TRI-STATE buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation. Truth Table Inputs MR L H H H H S1 X H L H L S0 X H H L L CP X N N N Response Asynchronous Reset; Q0–Q7 = LOW Parallel Load; I/On → Qn Shift Right; DS0 → Q0, Q0 → Q1, etc. Shift Left, DS7 → Q7, Q7 → Q6, etc. Hold X H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial N = LOW-to-HIGH Transition www.national.com 2 Logic Diagram DS100252-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.national.com Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC +0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC +0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current Per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC +0.5V −20 mA +20 mA −0.5V to VCC +0.5V Recommended Operating Conditions Supply Voltage (VCC) (Unless Otherwise Specified) ’AC ’ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54AC/ACT Minimum Input Edge Rate (∆V/∆t) ’AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (∆V/∆t) ’ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 2.0V to 6.0V 4.5V to 5.0V 0V to VCC 0V to VCC −55˚C to +125˚C ±50 mA ±50 mA −65˚C to +150˚C 175˚C 125 mV/ns 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. Obviously the databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications. DC Electrical Characteristics For ’AC Family Devices Symbol Parameter VCC (V) VIH Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage VOH Minimum High Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 54AC TA = −55˚C to +125˚C Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 (Note 2) VIN = VIL or VIH IOH = −12 mA IOH = −24 mA IOH = −24 mA IOUT = 50 µA V (Note 2) VIN = VIL or VIH IOH = 12 mA V µA IOH = 24 mA IOH = 24 mA VI = VCC, GND V IOUT = −50 µA V VOUT = 0.1V or VCC − 0.1V V VOUT = 0.1V or VCC − 0.1V Units Conditions 3.0 4.5 5.5 VOL Maximum Low Level Output Voltage 3.0 4.5 5.5 2.4 3.7 4.7 0.1 0.1 0.1 V 3.0 4.5 5.5 IIN Maximum Input Leakage Current Note 2: All outputs loaded; threshold on input associated with output under test. 0.50 0.50 0.50 5.5 ±1.0 www.national.com 4 DC Electrical Characteristics For ’AC Family Devices Symbol Parameter VCC (V) (Note 4) IOLD IOHD ICC IOZT Minimum Dynamic Output Current Maximum Quiescent Supply Current Maximum I/O Leakage Current 5.5 5.5 5.5 5.5 50 −50 80.0 mA mA µA VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND VI(OE) = VIL, VIH VI = VCC, GND VO = VCC, GND Note 3: All outputs loaded; threshold on input associated with output under test. Note 4: Maximum test duration 20 ms, one output loaded at a time. Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ICC for 54AC @ 25˚C is identical to 74AC @ 25˚C. 54AC TA = −55˚C to +125˚C Guaranteed Limits Units Conditions ±5.5 µA DC Electrical Characteristics For ’ACT Family Devices Symbol Parameter VCC (V) VIH VIL VOH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level 4.5 5.5 3.0 4.5 4.5 5.5 54ACT TA = −55˚C to +125˚C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 (Note 7) VIN = VIL or VIH IOH = −24 mA IOH = −24 mA IOUT = 50 µA (Note 7) VIN = VIL or VIH IOL = 24 mA IOL = 24 mA VI = VCC, GND VI = VCC − 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND VI(OE) = VIL, VIH VI = VCC, GND VO = VCC, GND V V VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA Units Conditions 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 3.70 4.70 0.1 0.1 V V 4.5 5.5 IIN ICCT IOLD IOHD ICC IOZT Maximum Input Leakage Current Maximum ICC/Input (Note 8) Minimum Dynamic Output Current Maximum Quiescent Supply Current Maximum I/O Leakage Current 5.5 5.5 5.5 5.5 5.5 5.5 0.50 0.50 V µA mA mA mA µA ±1.0 1.6 50 −50 80.0 ±5.0 µA 5 www.national.com DC Electrical Characteristics (Continued) Note 6: ICC limit for 54ACT @ 25˚C is identical to 74ACT @ 25˚C. Note 7: All outputs loaded; thresholds on input associated with output under test. Note 8: Maximum test duration 2.0 ms, one output loaded at a time. Capacitance Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 170 Units pF pF Conditions VCC = 5.0V VCC = 5.5V AC Electrical Characteristics VCC Symbol Parameter (V) (Note 9) Min fmax tPLH Maximum Input Frequency Propagation Delay CP to Q0 or Q7 (Shift Left or Right) tPHL Propagation Delay CP to Q0 or Q7 (Shift Left or Right) tPLH tPHL tPHL tPHL tPZH tPZL tPHZ tPLZ Propagation Delay CP to I/On Propagation Delay CP to I/On Propagation Delay MR to Q0 or Q7 Propagation Delay MR to I/On Output Enable Time OE to I/On Output Enable Time OE to I/On Output Disable Time OE to I/On Output Disable Time OE to I/On Note 9: Voltage Range 3.3 is 3.3V ±0.3V. Voltage Range 5.0 is 5.0V ±0.5V. 54AC TA = −55˚C to +125˚C CL = 50 pF Max MHz 25.5 17.5 26.5 18.0 24.5 17.0 26.5 18.5 27.0 18.5 26.5 18.0 22.0 15.0 23.5 16.0 22.5 17.0 21.5 16.0 ns ns ns ns ns ns ns ns ns ns 70 80 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Units Fig. No. 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 www.national.com 6 AC Operating Requirements VCC Symbol Parameter (V) (Note 10) 54AC TA = −55˚C to +125˚C CL = 50 pF Guaranteed Minimum ts th ts th ts th tw tw trec Setup Time, HIGH or LOW S0 or S1 to CP Hold Time, HIGH or LOW S0 or S1 to CP Setup Time, HIGH or LOW I/On to CP Hold Time, HIGH or LOW I/On to CP Setup Time, HIGH or LOW DS0 or DS7 to CP Hold Time, HIGH or LOW DS0 or DS7 to CP CP Pulse Width, LOW MR Pulse Width, LOW Recovery Time MR to CP Note 10: Voltage Range 3.3 is 3.3V ±0.3V Voltage Range 5.0 is 5.0V ±0.5V Fig. Units No. 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 9.5 7.0 2.0 2.5 6.0 4.0 1.5 2.0 7.5 5.0 1.5 1.5 5.5 5.0 5.5 5.0 2.5 2.5 ns ns ns ns ns ns ns ns ns AC Electrical Characteristics VCC Symbol Parameter (V) (Note 11) Min fmax tPLH Maximum Input Frequency Propagation Delay CP to Q0 or Q7 (Shift Left or Right) tPHL Propagation Delay CP to Q0 or Q7 (Shift Left or Right) tPLH tPHL tPHL tPHL Propagation Delay CP to I/On Propagation Delay CP to I/On Propagation Delay MR to Q0 or Q7 Propagation Delay MR to I/On 5.0 1.0 17.5 ns 5.0