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Part Number |
54ACT253 |
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Manufacturer |
National Semiconductor |
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Semiconductor DataSheet |
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DataSheet View |
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54AC253 • 54ACT253 Dual 4-Input Multiplexer with TRI-STATE Outputs
August 1998
54AC253 • 54ACT253 Dual 4-Input Multiplexer with TRI-STATE ® Outputs
General Description
The ’AC/’ACT253 is a dual 4-input multiplexer with TRI-STATE outputs. It can select two bits of data from four sources using common select inputs. The outputs may be individually switched to a high impedance state with a HIGH on the respective Output Enable (OE) inputs, allowing the outputs to interface directly with bus oriented systems. n n n n n Multifunction capability Noninverting TRI-STATE outputs Outputs source/sink 24 mA ’ACT253 has TTL-compatible inputs Standard Military Drawing (SMD) — ’AC253: 5962-87693 — ’ACT253: 5962-87761
Features
n ICC and IOZ reduced by 50%
Logic Diagrams
IEEE/IEC
DS100285-1
DS100285-2
Pin Names I0a–I3a I0b–I3b S0, S1 OEa OEb Za, Zb
Description Side A Data Inputs Side B Data Inputs Common Select Inputs Side A Output Enable Input Side B Output Enable Input TRI-STATE Outputs
TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT ® is a registered trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100285
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Connection Diagrams
Pin Assignment for DIP and Flatpak Pin Assignment for LCC
DS100285-3 DS100285-4
Functional Description
The ’AC/’ACT253 contains two identical 4-input multiplexers with TRI-STATE outputs. They select two bits from four sources selected by common Select inputs (S0, S1). The 4-input multiplexers have individual Output Enable (OEa, OEb) inputs which, when HIGH, force the outputs to a high impedance (High Z) state. This device is the logic implementation of a 2-pole, 4-position switch, where the position of the switch is determined by the logic levels supplied to the two select inputs. The logic equations for the outputs are shown: Za = OEa • (I0a • S1 • S0 + I1a • S1 • S0 + I2a • S1 • S0 + I3a • S1 • S0) Zb = OEb • (I0b • S1 • S0 + I1b • S1 • S0 + I2b • S1 • S0 + I3b • S1 • S0) If the outputs of TRI-STATE devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure that Output Enable signals to TRI-STATE devices whose outputs are tied together are designed so that there is no overlap.
Truth Table
Select Inputs S0 X L L H H L L H H S1 X L L L L H H H H I0 X L H X X X X X X I1 X X X L H X X X X I2 X X X X X L H X X I3 X X X X X X X L H Data Inputs Output Enable OE H L L L L L L L L Z Z L H L H L H L H Outputs
Address Inputs S0 and S1 are common to both sections. H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance
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Logic Diagram
DS100285-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V
Recommended Operating Conditions
Supply Voltage (VCC) ’AC ’ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54AC/ACT Minimum Input Edge Rate (∆V/∆t) ’AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (∆V/∆t) ’ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C
125 mV/ns
±50 mA ±50 mA −65˚C to +150˚C
175˚C
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications.
DC Characteristics for ’AC Family Devices
Symbol Parameter VCC (V) VIH Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage VOH Minimum High Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 54AC TA = −55˚C to +125˚C Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 (Note 2) VIN = VIL or VIH IOH = −12 mA IOH = −24 mA IOH = −24 mA IOUT = 50 µA V (Note 2) VIN = VIL or VIH IOL = 12 mA V µA IOL = 24 mA IOL = 24 mA VI = VCC, GND VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND V IOUT = −50 µA V VOUT = 0.1V or VCC − 0.1V V VOUT = 0.1V or VCC − 0.1V Units Conditions
3.0 4.5 5.5 VOL Maximum Low Level Output Voltage 3.0 4.5 5.5
2.4 3.7 4.7 0.1 0.1 0.1 V
3.0 4.5 5.5 IIN IOZ Maximum Input Leakage Current Maximum TRI-STATE Current 5.5 5.5
0.50 0.50 0.50
±1.0
±5.0
µA
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DC Characteristics for ’AC Family Devices
Symbol Parameter VCC (V) (Note 3) IOLD IOHD ICC Minimum Dynamic Output Current Maximum Quiescent Supply Current
Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
(Continued)
54AC TA = −55˚C to +125˚C Guaranteed Limits
Units
Conditions
5.5 5.5 5.5
50 −50 80.0
mA mA µA
VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ICC for 54AC @ 25˚C is identical to 74AC @ 25˚C.
DC Characteristics for ’ACT Family Devices
Symbol Parameter VCC (V) VIH VIL VOH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage 4.5 5.5 4.5 5.5 4.5 5.5 54ACT TA = −55˚C to +125˚C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 (Note 5) VIN = VIL or VIH IOH = −24 mA IOH = −24 mA IOUT = 50 µA (Note 5) VIN = VIL or VIH IOL = 24 mA IOL = 24 mA VI = VCC, GND VI = VIL, VIH VO = VCC, GND VI = VCC − 2.1V V V V VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA Units Conditions
4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5
3.70 4.70 0.1 0.1
V V
4.5 5.5 IIN IOZ ICCT Maximum Input Leakage Current Maximum TRI-STATE Current Maximum ICC/Input (Note 6) IOLD IOHD ICC Minimum Dynamic Output Current Maximum Quiescent Supply Current
Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. Note 7: ICC for 54ACT @ 25˚C is identical to 74ACT @ 25˚C.
0.50 0.50
V µA µA mA
5.5 5.5 5.5
±1.0 ±5.0
1.6
5.5 5.5 5.5
50 −50 80.0
mA mA µA
VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND
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AC Electrical Characteristics
VCC Symbol Parameter (V) (Note 8) tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay Sn to Zn Propagation Delay Sn to Zn Propagation Delay In to Zn Propagation Delay In to Zn Output Enable Time Output Enable Time Output Disable Time Output Disable Time 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
Note 8: Voltage Range 3.3 is 3.3V ±0.3V Voltage Range 5.0 is 5.0V ±0.5V
54AC TA = −55˚C to +125˚C CL = 50 pF Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 18.0 12.5 18.5 13.5 17.0 11.5 15.0 11.5 9.0 7.0 9.5 8.0 10.5 9.0 9.5 8.0 ns ns ns ns ns ns ns ns Units
Fig. No.
AC Electrical Characteristics
VCC Symbol Parameter (V) (Note 9) tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay Sn to Zn Propagation Delay Sn to Zn Propagation Delay In to Zn Propagation Delay In to Zn Output Enable Time Output Enable Time Output Disable Time Output Disable Time 5.0 5.0 5.0 5.0 1.0 1.0 1.0 1.0 9.5 9.5 11.0 9.0 ns ns ns ns 5.0 1.0 13.5 ns 5.0 1.0 12.0 ns 5.0 1.0 16.0 ns 5.0 1.0 54ACT TA = −55˚C to +125˚C CL = 50 pF Min Max 14.5 ns Units Fig. No.
Note 9: Voltage Range 5.0 is 5.0V ±0.5V
Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 50.0 Units pF pF Conditions VCC = OPEN VCC = 5.0V
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Physical Dimensions
inches (millimeters) unless otherwise noted
20 Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A
16 Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A
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54AC253 • 54ACT253 Dual 4-Input Multiplexer with TRI-STATE Outputs
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
16 Lead Ceramic Flatpak (F) NS Package Number W16A
LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
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