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Part Number |
54ACT251 |
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Manufacturer |
National Semiconductor |
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Semiconductor DataSheet |
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DataSheet View |
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54AC251 • 54ACT251 8-Input Multiplexer with TRI-STATE Output
August 1998
54AC251 • 54ACT251 8-Input Multiplexer with TRI-STATE ® Output
General Description
The ’AC/’ACT251 is a high-speed 8-input digital multiplexer. It provides, in one package, the ability to select one bit of data from up to eight sources. It can be used as universal function generator to generate any logic function of four variables. Both true and complementary outputs are provided. n n n n n n Multifunctional capability On-chip select logic decoding Inverting and noninverting TRI-STATE outputs Outputs source/sink 24 mA ’ACT251 has TTL-compatible inputs Standard Military Drawing (SMD) — ’AC251: 5962-87692 — ’ACT251: 5962-89599
Features
n ICC reduced by 50%
Logic Symbols
IEEE/IEC
DS100284-1
DS100284-2
Pin Names S0–S2 OE I0–I7 Z Z Select Inputs
Description TRI-STATE Output Enable Input Multiplexer Inputs TRI-STATE Multiplexer Output Complementary TRI-STATE Multiplexer Output
TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT ® is a registered trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100284
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Connection Diagrams
Pin Assignment for DIP and Flatpak
Functional Description
This device is a logical implementation of a single-pole, 8-position switch with the switch position controlled by the state of three Select inputs, S0, S1, S2. Both true and complementary outputs are provided. The Output Enable input ( OE) is active LOW. When it is activated, the logic function provided at the output is: Z = OE • (I0 • S0 • S1 • S2 + I1 • S0 • S1 • S 2 + I 2 • S 0 • S 1 • S2 + I 3 • S 0 • S1 • S2 + I 4 • S0 • S1 • S2 + I 5 • S 0 • S1 • S2 + I6 • S0 • S 1 • S2 + I7 • S0 • S1 • S2) When the Output Enable is HIGH, both outputs are in the high impedance (High Z) state. This feature allows multiplexer expansion by tying the outputs of up to 128 devices together. When the outputs of the TRI-STATE devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. The Output Enable signals should be designed to ensure there is no overlap in the active-LOW portion of the enable voltages.
DS100284-3
Pin Assignment for LCC
Truth Table
Inputs OE H L L L L
DS100284-4
Outputs S1 X L L H H L L H H S0 X L H L H L H L H Z Z I0 I1 I2 I3 I4 I5 I6 I7 Z Z I0 I1 I2 I3 I4 I5 I6 I7
S2 X L L L L H H H H
L L L L
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance
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Logic Diagram
DS100284-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V
Recommended Operating Conditions
Supply Voltage (VCC) ’AC ’ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54AC/ACT Minimum Input Edge Rate (∆V/∆t) ’AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (∆V/∆t) ’ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C
125 mV/ns
±50 mA ±50 mA −65˚C to +150˚C
175˚C
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications. Note 2: All outputs loaded; thresholds on input associated with output under test.
DC Characteristics for ’AC Family Devices
Symbol VIH Parameter Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage VOH Minimum High Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 54AC TA = −55˚C to +125˚C Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 (Note 2) VIN = VIL or VIH 3.0 4.5 5.5 VOL Maximum Low Level Output Voltage 3.0 4.5 5.5 2.4 3.7 4.7 0.1 0.1 0.1 (Note 2) VIN = VIL or VIH 3.0 4.5 5.5 IIN Maximum Input Leakage Current 5.5 0.50 0.50 0.50 V µA IOL = 12 mA IOL = 24 mA IOL = 24 mA VI = VCC, GND V V IOH = −12 mA IOH = −24 mA IOH = −24 mA IOUT = 50 µA V IOUT = −50 µA V VOUT = 0.1V or VCC − 0.1V V VOUT = 0.1V or VCC − 0.1V Units Conditions
±1.0
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DC Characteristics for ’AC Family Devices
Symbol IOZ Parameter Maximum TRI-STATE Current IOLD IOHD ICC Minimum Dynamic Output Current (Note 3) Maximum Quiescent Supply Current
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
(Continued)
VCC (V) 5.5 5.5 5.5 5.5
54AC TA = −55˚C to +125˚C Guaranteed Limits
Units
Conditions VI (OE) = VIL, VIH VI = VCC, VGND VO = VCC, GND VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND
±5.0
50 −50 80.0
µA mA mA µA
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ICC for 54AC @ 25˚C is identical to 74AC @ 25˚C.
DC Characteristics for ’ACT Family Devices
Symbol VIH VIL VOH Parameter Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 54ACT TA = −55˚C to +125˚C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 (Note 5) VIN = VIL or VIH 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 3.70 4.70 0.1 0.1 (Note 5) VIN = VIL or VIH 4.5 5.5 IIN IOZ ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum TRI-STATE Current Maximum ICC/Input Minimum Dynamic Output Current (Note 6) Maximum Quiescent Supply Current
Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. Note 7: ICC for 54ACT @ 25˚C is identical to 74ACT @ 25˚C.
Units V V V
Conditions VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA
V V
IOH = −24 mA IOH = −24 mA IOUT = 50 µA
0.50 0.50
V µA µA mA mA mA µA
IOL = 24 mA IOL = 24 mA VI = VCC, GND VI = VIL, VIH VO = VCC, GND VI = VCC − 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND
5.5 5.5 5.5 5.5 5.5 5.5
±1.0 ±5.0
1.6 50 −50 80.0
5
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AC Electrical Characteristics
VCC Symbol Parameter (V) (Note 8) Min tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay Sn to Z or Z Propagation Delay Sn to Z or Z Propagation Delay In to Z or Z Propagation Delay In to Z or Z Output Enable Time OE to Z or Z Output Enable Time OE to Z or Z Output Disable Time OE to Z or Z Output Disable Time OE to Z or Z
Note 8: Voltage Range 3.3 is 3.3V ±0.3V Voltage Range 5.0 is 5.0V ±0.5V
54AC TA = −55˚C to +125˚C CL = 50 pF Max 21.0 15.5 21.0 15.5 17.0 12.0 16.5 12.0 13.0 10.0 13.0 10.0 14.0 11.0 13.0 10.0 ns ns ns ns ns ns ns ns 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 3.5 2.5 4.0 3.0 Units
3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
AC Electrical Characteristics
VCC Symbol Parameter (V) (Note 9) Min tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay Sn to Z or Z Propagation Delay Sn to Z or Z Propagation Delay In to Z or Z Propagation Delay In to Z or Z Output Enable Time OE to Z or Z Output Enable Time OE to Z or Z Output Disable Time OE to Z or Z Output Disable Time OE to Z or Z
Note 9: Voltage Range 5.0 is 5.0V ±0.5V
54ACT TA = −55˚C to +125˚C CL = 50 pF Max 18.0 18.0 13.5 13.5 10.0 9.5 12.5 8.5 ns ns ns ns ns ns ns ns 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Units
5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0
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Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 70.0 Units pF pF Conditions VCC = OPEN VCC = 5.0V
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Physical Dimensions
inches (millimeters) unless otherwise noted
20 Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A
16 Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A
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54AC251 • 54ACT251 8-Input Multiplexer with TRI-STATE Output
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
16 Lead Ceramic Flatpak (F) NS Package Number W16A
LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
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