Up/Down Counter

www.DataSheet4U.com 54AC191 Up/Down Counter with Preset and Ripple Clock July 1998 54AC191 Up/Down Counter with Preset and Ripple Clock General Description The ’AC191 is a reversible modulo 16 binary counter. It features synchronous counting and asynchronous presetting. The preset feature allows the ’AC191 to be used in programmable dividers. The Count Enable input, the Terminal Count output and the Ripple Clock output make possible a variety of methods of implementing multistage counters. In the counting modes, state changes are initiated by the rising edge of the clock. Features n n n n n n n ICC reduced by 50% High speed — 133 MHz typical count frequency Synchronous counting Asynchronous parallel load Cascadable Outputs source/sink 24 mA Standard Military Drawing (SMD) — ’AC191: 5962-89749 Logic Symbols Connection Diagrams Pin Assignment for DIP and Flatpack DS100279-1 IEEE/IEC DS100279-3 Pin Assignment for LCC DS100279-2 Pin Names CE CP P0–P3 PL U/D Q0–Q3 RC TC Description Count Enable Input Clock Pulse Input Parallel Data Inputs Asynchronous Parallel Load Input Up/Down Count Control Input Flip-Flop Outputs Ripple Clock Output Terminal Count Output DS100279-4 FACT™ is a trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100279 www.national.com Functional Description The ’AC191 is a synchronous up/down counter. The ’AC191 is organized as a 4-bit binary counter. It contains four edge-triggered flip-flops with internal gating and steering logic to provide individual preset, count-up and count-down operations. Each circuit has an asynchronous parallel load capability permitting the counter to be preset to any desired number. When the Parallel Load (PL) input is LOW, information present on the Parallel Load inputs (P0–P3) is loaded into the counter and appears on the Q outputs. This operation overrides the counting functions, as indicated in the Mode Select Table. A HIGH signal on the CE input inhibits counting. When CE is LOW, internal state changes are initiated synchronously by the LOW-to-HIGH transition of the clock input. The direction of counting is determined by the U/D input signal, as indicated in the Mode Select Table. CE and U/D can be changed with the clock in either state, provided only that the recommended setup and hold times are observed. Two types of outputs are provided as overflow/underflow indicators. The terminal count (TC) output is normally LOW. It goes HIGH when the circuits reach zero in the count down mode or 15 in the count up mode. The TC output will then remain HIGH until a state change occurs, whether by counting or presetting or until U/D is changed. The TC output should not be used as a clock signal because it is subject to decoding spikes. The TC signal is also used internally to enable the Ripple Clock (RC) output. The RC output is normally HIGH. When CE is LOW and TC is HIGH, RC output wil go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again. This feature simplifies the design of multistage counters, as indicated in Figure 1 and Figure 2. In Figure 1, each RC output is used as the clock input for the next higher stage. This configuration is particularly advantageous when the clock source has a limited drive capability, since it drives only the first stage. To prevent counting in all stages it is only necessary to inhibit the first stage, since a HIGH signal on CE inhibits the RC output pulse, as indicated in the RC Truth Table. A disadvantage of this configuration, in some applications, is the timing skew between state changes in the first and last stages. This represents the cumulative delay of the clock as it ripples through the preceding stages. A method of causing state changes to occur simultaneously in all stages is shown in Figure 2. All clock inputs are driven in parallel and the RC outputs propagate the carry/borrow signals in ripple fashion. In this configuration the LOW state duration of the clock must be long enough to allow the negative-going edge of the carry/borrow signal to ripple through to the last stage before the clock goes HIGH. There is no such restriction on the HIGH state duration of the clock, since the RC output of any device goes HIGH shortly after its CP input goes HIGH. The configuration shown in Figure 3 avoids ripple delays and their associated restrictions. The CE input for a given stage is formed by combining the TC signals from all the preceding stages. Note that in order to inhibit counting an enable signal must be included in each carry gate. The simple inhibit scheme of Figure 1 and Figure 2 doesn’t apply, because the TC output of a given stage is not affected by its own CE. Mode Select Table Inputs PL H H L H CE L L X H U/D L H X X CP N N Mode Count Up Count Down Preset (Asyn.) No Change (Hold) X X RC Truth Table Inputs PL H H H L CE L H X X TC* H X L X CP J Outputs RC J X X X H H H *TC is generated internally H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial N = LOW-to-HIGH Transition www.national.com 2 Functional Description (Continued) DS100279-7 FIGURE 1. N-Stage Counter Using Ripple Clock DS100279-8 FIGURE 2. Synchronous N-Stage Counter Using Ripple Carry/Borrow DS100279-9 FIGURE 3. Synchronous N-Stage Counter with Parallel Gated Carry/Borrow 3 www.national.com State Diagram DS100279-5 Logic Diagram DS100279-6 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 4 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V Junction Temperature (TJ) CDIP 175˚C Recommended Operating Conditions Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54AC Minimum Input Edge Rate (∆V/∆t) ’AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V 4.5V, 5.5V 2.0V to 6.0V 0V to VCC 0V to VCC −55˚C to +125˚C ± 50 mA ± 50 mA −65˚C to +150˚C 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, output/input loading variables. National does not recommend operation of FACT™ circuits outside databook specifications. DC Characteristics for ’AC Family Devices Symbol VIH Parameter Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage VCC (V) 3.0 4.5 5.5 VIL 3.0 4.5 5.5 VOH 3.0 4.5 5.5 54AC TA = −55˚C to +125˚C Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 (Note 2) VIN = VIL or VIH 3.0 4.5 5.5 VOL Maximum Low Level Output Voltage 3.0 4.5 5.5 2.4 3.7 4.7 0.1 0.1 0.1 (Note 2) VIN = VIL or VIH 3.0 4.5 5.5 IIN IOLD IOHD ICC Maximum Input Leakage Current (Note 3) Minimum Dynamic Output Current Maximum Quiescent Supply Current 5.5 5.5 5.5 50 −50 80.0 mA mA µA VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND 5.5 0.50 0.50 0.50 V µA VI = VCC, GND 12 mA IOL 24 mA 24 mA V IOUT = 50 µA V −12 mA IOH −24 mA −24 mA V IOUT = −50 µA V VOUT = 0.1V or VCC − 0.1V V VOUT = 0.1V or VCC − 0.1V Units Conditions ± 1.0 5 www.national.com DC Characteristics for ’AC Family Devices Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. (Continued) Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ICC for 54AC @ 25˚C is identical to 74AC @ 25˚C. AC Electrical Characteristics 54AC VCC Symbol Parameter (V) (Note 5) Min fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Maximum Count Frequency Propagation Delay CP to Qn Propagation Delay CP to Qn Propagation Delay CP to TC Propagation Delay CP to TC Propagation Delay CP to RC Propagation Delay CP to RC Propagation Delay CE to RC Propagation Delay CE to RC Propagation Delay U/D to RC Propagation Delay U/D to RC Propagation Delay U/D to TC Propagation Delay U/D to TC Propagation Delay Pn to Qn Propagation Delay Pn to Qn Propagation Delay PL to Qn Propagation Delay PL to Qn Note 5: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V TA = −55˚C to +125˚C CL = 50 pF Max 55 80 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 16.5 12.0 16.0 12.0 19.5 14.0 19.0 14.5 14.0 10.5 12.5 9.5 14.0 10.0 12.5 9.5 14.5 11.0 15.0 11.0 14.0 10.5 13.5 10.0 16.5 11.5 15.5 10.5 18.0 12.5 15.5 11.5 Units Fig. No. 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns www.national.com 6 AC Operating Requirements 54AC VCC (V) (Note 6) TA = −55˚C to +125˚C CL = 50 pF Guaranteed Minimum 4.0 3.0 1.5 2.0 9.0 6.0 0 0.5 10.5 7.5 0 1.0 5.0 5.0 6.0 6.0 1.5 1.0 ns ns ns ns ns ns ns ns ns Fig. No. Symbol Parameter Units ts th ts th ts th tw tw trec Setup Time, HIGH or LOW Pn to PL Hold Time, HIGH or LOW Pn to PL Setup Time, LOW CE to CP Hold Time, LOW CE to CP Setup Time, HIGH or LOW U/D to CP Hold Time, HIGH or LOW U/D to CP PL Pulse Width, LOW CP Pulse Width, LOW Recovery Time PL to CP 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.