Quad D Flip-Flop

www.DataSheet4U.com 54AC175 • 54ACT175 Quad D Flip-Flop August 1998 54AC175 • 54ACT175 Quad D Flip-Flop General Description The ’AC/’ACT175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, when LOW. n n n n n n Buffered positive edge-triggered clock Asynchronous common reset True and complement output Outputs source/sink 24 mA ’ACT175 has TTL-compatible inputs Standard Microcircuit Drawing (SMD) — ’AC175: 5962-89552 — ’ACT175: 5962-89693 Features n Edge-triggered D-type inputs Logic Symbols Connection Diagrams Pin Assignment for DIP and Flatpak DS100278-1 IEEE/IEC DS100278-3 Pin Assignment for LCC DS100278-2 Pin Names D0–D3 CP MR Q0–Q3 Q0–Q3 Description Data Inputs Clock Pulse Input Master Reset Input True Outputs Complement Outputs DS100278-4 FACT ® is a registered trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100278 www.national.com Functional Description The ’AC/’ACT175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the LOW-to-HIGH clock (CP) transition, causing individual Q and Q outputs to follow. A LOW input on the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs. The ’AC/’ACT175 is useful for general logic applications where a common Master Reset and Clock are acceptable. Truth Table Inputs @ tn, MR = H Outputs @ tn+1 Dn L H H = HIGH Voltage Level L = LOW Voltage Level tn = Bit Time before Clock Pulse tn+1 = Bit Time after Clock Pulse Qn L H Qn H L Logic Diagram DS100278-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V Recommended Operating Conditions Supply Voltage (VCC) ’AC ’ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54AC/ACT Minimum Input Edge Rate (∆V/∆t) ’AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (∆V/∆t) ’ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns ±50 mA ±50 mA −65˚C to +150˚C 175˚C 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications. DC Characteristics for ’AC Family Devices Symbol VIH Parameter Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage VOH Minimum High Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 54AC TA = −55˚C to +125˚C Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 (Note 2) VIN = VIL or VIH IOH = −12 mA V IOH = −24 mA IOH = −24 mA IOUT = 50 µA V IOUT = −50 µA V VOUT = 0.1V or VCC − 0.1V V VOUT = 0.1V or VCC − 0.1V Units Conditions 3.0 4.5 5.5 VOL Maximum Low Level Output Voltage 3.0 4.5 5.5 2.4 3.7 4.7 0.1 0.1 0.1 V 3.0 4.5 5.5 IIN Maximum Input Leakage Current (Note 3) IOLD IOHD Minimum Dynamic Output Current 5.5 5.5 5.5 0.50 0.50 0.50 V µA (Note 2) VIN = VIL or VIH IOL = 12 mA IOL = 24 mA IOL = 24 mA VI = VCC, GND ±1.0 50 −50 mA mA VOLD = 1.65V Max VOHD = 3.85V Min 3 www.national.com DC Characteristics for ’AC Family Devices Symbol ICC Parameter Maximum Quiescent Supply Current Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. (Continued) VCC (V) 5.5 54AC TA = −55˚C to +125˚C Guaranteed Limits 160.0 Units µA Conditions VIN = VCC or GND Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ICC for 54AC @ 25˚C is identical to 74AC @ 25˚C. DC Characteristics for ’ACT Family Devices Symbol VIH VIL VOH Parameter Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 54ACT TA = −55˚C to +125˚C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 (Note 5) VIN = VIL or VIH IOH = −24 mA IOH = −24 mA IOUT = 50 µA (Note 5) VIN = VIL or VIH IOL = 24 mA IOL = 24 mA VI = VCC, GND VI = VCC − 2.1V V V V VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA Units Conditions 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 3.70 4.70 0.1 0.1 V V 4.5 5.5 IIN ICCT Maximum Input Leakage Current Maximum ICC/Input (Note 6) IOLD IOHD ICC Minimum Dynamic Output Current Maximum Quiescent Supply Current Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. Note 7: ICC for 54ACT @ 25˚C is identical to 74ACT @ 25˚C. 0.50 0.50 V µA mA 5.5 5.5 ±1.0 1.6 5.5 5.5 5.5 50 −50 160.0 mA mA µA VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND www.national.com 4 AC Electrical Characteristics Symbol Parameter VCC (V) (Note 8) fmax tPLH tPHL tPLH tPHL Maximum Clock Frequency Propagation Delay CP to Qn or Qn Propagation Delay CP to Qn or Qn Propagation Delay MR to Qn Propagation Delay MR to Qn Note 8: Voltage Range 3.3 is 3.3V ±0.3V Voltage Range 5.0 is 5.0V ±0.5V 54AC TA = −55˚C to +125˚C CL = 50 pF Min 95 95 1.0 1.5 1.0 1.5 1.0 1.5 1.0 1.5 14.5 10.5 15.0 11.5 15.0 11.0 13.5 10.5 Max Units Fig. No. 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 MHz ns ns ns ns AC Operating Requirements Symbol Parameter VCC (V) (Note 9) ts th tw tw trec Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP CP Pulse Width HIGH or LOW MR Pulse Width, LOW Recovery Time MR to CP Note 9: Voltage Range 3.3 is 3.3V ±0.3V Voltage Range 5.0 is 5.0V ±0.5V 54AC TA = −55˚C to +125˚C CL = 50 pF Guaranteed Minimum 5.0 3.5 2.0 2.5 6.0 5.0 5.5 5.0 1.5 1.5 Units Fig. No. 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 ns ns ns ns ns 5 www.national.com AC Electrical Characteristics Symbol Parameter VCC (V) (Note 10) fmax tPLH tPHL tPLH tPHL Maximum Clock Frequency Propagation Delay CP to Qn or Qn Propagation Delay CP to Qn or Qn Propagation Delay MR to Qn Propagation Delay MR to Qn Note 10: Voltage Range 5.0 is 5.0V ±0.5V 54ACT TA = −55˚C to +125˚C CL = 50 pF Min 95 1.5 1.5 1.5 1.5 11.5 12.5 11.5 11.0 Max Units Fig. No. 5.0 5.0 5.0 5.0 5.0 MHz ns ns ns ns AC Operating Requirements Symbol Parameter VCC (V) (Note 11) ts (H) ts (L) th tw tw trec Setup Time Dn to CP Hold Time, HIGH or LOW Dn to CP CP Pulse Width HIGH or LOW MR Pulse Width, LOW Recovery Time, MR to CP 5.0 5.0 5.0 1.5 ns ns 5.0 5.0 ns 5.0 5.0 54ACT TA = −55˚C to +125˚C CL = 50 pF Guaranteed Minimum 3.5 3.5 1.5 ns ns Units Fig. No. Note 11: Voltage Range 5.0 is 5.0V ±0.5V Capacitance Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 45.0 Units pF pF Conditions VCC = OPEN VCC = 5.0V www.national.com 6 Physical Dimensions inches (millimeters) unless otherwise noted 20 Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A 16-Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A 7 www.national.com 54AC175 • 54ACT175 Quad D Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Ceramic Flatpak (F) NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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